Scaling core clock of 100MHz to 23MHz & 20MHz

[Altera_Forum]

Hello All, 

 I am using Altera Stratix II for my project. I have generated a PLL in LVDs mode(for a deserialization factor of 10 and date rates is 1000Mbps). The two available clock sources on the board are 100MHz and 62.5MHz. I need to generate 23MHz and 20MHz MHz clocks for a module in my project.  When I try to generate a PLL in LVDs mode in Mega Core Wizard, by default it selects a FAST PLL and the minimum output frequency is 33.3333MHz.  Can I use any other logic and generate a 23MHz and 20MHz clock from 100MHz core clock. Can any one of you suggest a solution to this problem.  Many thanks in advance,

[Altera_Forum]

Hiii!!1 

 The problem I have is clearly mentioned in page 17–12 and 17 -13 for the Stratix GX (please find below) document..... Thku very much... The only solution is to use a State Machine as mentioned by u in ur previous reply. Thku once again. So nice of u.   http://www.altera.com/literature/hb/sgx/sgx_sgx52013.pdf  lg, Sa

[Altera_Forum]

As far as I experienced, ModelSim simulation of LVDS receivers and DPA was almost matching the real chip behaviour. 

 I understand that you are particularly referring to the word boundary integrity problem discussed in the manual. To my opinion, the issue only occurs if the correct alignment position is near to the initial position. In this case, some channels may need zero alignment pulses and some channel would need -1 pulse. Cause no negative shift is possible, these channel's phase is advanced by n-1 bit positions (n is the deserialization factor), crossing the word boundary.   If the typical aligned phase is in the middle of DPA range, this never happens. So I don't think that it's necessary to check the word integrity in the DPA logic, which could be done e.g. by using a two word (alternating) train pattern.

[Altera_Forum]

I tried with following code to align the word but its not working. I have taken "ready" signal to increment the address of the ram. Could you suggest any modifications?  

   Data_align : process (iRxClk,inUserReset)  -- variable count: integer:=1;  begin  if(inUserReset='0') then  rx_channel_data_align <= "0";    elsif(iRxClk'event and iRxClk='1') then  if (rx_channel_data_align = "1") then  rx_channel_data_align <= "0";  end if;   if(rx_dpa_locked="1") then    if (rx_out = "0100110101") then  rx_channel_data_align <= "0";  ready<='1';  else   rx_channel_data_align <= "1";  end if;  end if;    end if;  end process Data_align;

[Altera_Forum]

Your logic apparently drives out a square wave to rx_channel_data_align. This can't work, cause it leaves no time for the updated result to propagate to rx_out, as I mentioned previously. I'm allowing a new data_align pulse after 8 clocks, as you can see from my example code. To evaluate DPA operation, it may be meaningful to apply a single pulse only and observe the results in simulator or SignalTap.

[Altera_Forum]

Thank you. 

 Am using a deserialization factor of 10, iRxClk is 100 MHz slow clock which is the output of an external PLL. As you mentoined prevously that you are allowing new data_align pulse after 8 clocks, Could you please tell me which part of your design deals with the 8 clocks?  I have modified my code as below but there is no change yet.     Data_align : process (iRxClk,inUserReset)  variable count: integer:=1;  begin  if(inUserReset='0') then  rx_channel_data_align <= "0";    elsif(iRxClk'event and iRxClk='1') then  count:=count+1;  if(count=11) then  count:=0;  end if;    if (rx_channel_data_align = "1") then  rx_channel_data_align <= "0";    end if;   if(rx_dpa_locked="1") then  if(count=10) then  if (q_lpm = "0100110101") then  rx_channel_data_align <= "0";  ready<='1';   else   rx_channel_data_align <= "1";  end if;  end if;  end if;    end if;  end process Data_align;

[Altera_Forum]

The delay of 8 clocks is very similar to your code: 

if ((train_timer % 8) == 7 && rx_dpa_locked_sig) Another point is, that the DPA logic may require a reset.

[Altera_Forum]

Hi, 

 Have u used an External or internal PLL in ur design?

[Altera_Forum]

As I already mentioned I am using a two StratixII FPGA module board. When I send 10 bit data from Device1 to Device2 the bit was shifting as I mentioned earlier. But, with the help of state machine programme I have fixed this issue (Device1 to Device2 Data Transfer). 

 But, when I send data from Device2 to Device1 the bit is shifting is dynamic I mean if I send. 1111100000 continuously and read the data continuously in Device2 Ram the bit shifting is not static.  Sent 1111100000 Received 0111110000 (Device2 to Device1) Sent 1111100000 Received 0011111000(Device2 to Device1) Sent 1111100000 Received 0000111110(Device2 to Device1)  What can I do to fix this issue if the bit shifting is not static?

[Altera_Forum]

I assume that you are transmitting a suitable reference clock with the serial data link, that DPA is in hold and the data_alignment stopped. If so, a problem with reference clock or serial data signal quality may exist or any of the involved PLLs doesn't lock stable. 

 Provided, DPA had been set correct initially, you have a shift of minimal 2 ns, that's quite a lot. You should be able to identify the source of instability with an oscilloscope.

[Altera_Forum]

I am using an internal PLL with an input CLK of 100MHz and the data transfer at 1Gbps. But, with the same code the alignment works in one direstion (DUT1 to DUT2) but not from DUT2 to DUT1.

[Altera_Forum]

I think, it's different to say, the bit alignment is shifting (as you reported yesterday) or it's not working. The former means, it has been initially succesful but the alignment is unstable, the latter no alignment could be achieved. Tracing the alignment procedure with SignalTap, you should be able to reval what's actually going on. 

 As an additional remark, if a PLL looses lock, an areset is neccessary to restore the phase relation of outputs, this surely also apllies to LVDS transmitter/receiver PLL and DPA circuit. So it's necessary that the upstream clock supply has stabilized before performing DPA and bit alignment.

[Altera_Forum]

I am using a 2 Stratix II module board. The data transfer works perfectly in one direction DUT1 to DUT2(with asserting and deasserting rx_channel_data_align with the help of a State Machine ). But, when i repeat the same procedure from DUT2 to DUT1 it dosent work. I mean the bit shifting is dynamic.

[Altera_Forum]

Hi,  

 Can i please know, what kind of error detection and correction pattern have u used in ur design?

[Altera_Forum]

Don't think that the pattern matters much, as long as it's unequivocal. Four a four channel deserialisation, I used 0011.