Self reset to FPGA

[Altera_Forum]

Hi, 

 I'm integrating an independent FPGA which doesn't have a master CPU associated with it. I need to reset the FPGA right after it enters user mode. Will using Init_done signal Anded with Conf_done and looped back to a dedicated reset pin do the job? Am I missing something here? Should delay be added?  Thanks,  Boris Bakshan.

[Altera_Forum]

What are you trying to reset? Are you trying to wipe the FPGA? Or the user logic internally?

[Altera_Forum]

Hi, 

 The user logic in the code.

[Altera_Forum]

Hi Boris, 

  --- Quote Start ---   I need to reset the FPGA right after it enters user mode. Will using Init_done signal Anded with Conf_done and looped back to a dedicated reset pin do the job? Am I missing something here? Should delay be added?   --- Quote End ---    My preference is to route the CONF_DONE signal to the input of a reset supervisor IC. For example, see p95  http://www.ovro.caltech.edu/~dwh/carma_board/gda06rb004_carma_v0.87_dec03.pdf  The tri-state buffer is used to isolate CONF_DONE from the other reset sources.  Using a reset IC ensures that the reset signal is asserted for a reasonable amount of time. Inside the FPGA, the reset signal is synchronized to each of the different clock domains using the standard asynchronous assert, synchronous deassert scheme seen in various Altera documents (which derive from some Cliff Cummings papers on the subject).  Cheers, Dave

[Altera_Forum]

a slightly different tactic is to drive a counter from a clock you know will be active when the FPGA is configured. run the counter for the desired length of time (count value), and reset your user logic based on this signal. this is sometimes done to wait for the input clock to stabilize before coming out of user reset

[Altera_Forum]

--- Quote Start ---  a slightly different tactic is to drive a counter from a clock you know will be active when the FPGA is configured. run the counter for the desired length of time (count value), and reset your user logic based on this signal. this is sometimes done to wait for the input clock to stabilize before coming out of user reset  --- Quote End ---    But you see, the counter has got to have a reset condition. i.e it must be have a starting point but that is the problem... I have no reset condition to apply.

[Altera_Forum]

the counter can power up to 0 upon configuration. is there a reason that won't work?

[Altera_Forum]

--- Quote Start ---  the counter can power up to 0 upon configuration. is there a reason that won't work?  --- Quote End ---    In prinsiple it should work but altera recommends external reset. I think the reason is that it may fail occasionally due to clock hitting the registers when released from chip reset right after configuration leading to violation of recovery/removal with initial zero changing to unknown value which may freeze the counter or kick it after beyond decision point that generates user reset. A large counter then means less probability of failure.

[Altera_Forum]

can you point me to the docs where they recommend reset circuitry? 

 if there aren't any async signals to the reset counter, there isn't any recovery/removal to worry about, is there?  interesting discussion, thanks :)

[Altera_Forum]

--- Quote Start ---  can you point me to the docs where they recommend reset circuitry?  if there aren't any async signals to the reset counter, there isn't any recovery/removal to worry about, is there?  interesting discussion, thanks :)  --- Quote End ---    have a look here: http://www.altera.com/support/kdb/solutions/rd06112009_450.html  regarding reset,during POR all registers are held in reset of device then it is released. I assume this reset is applied through asynchronous port.  remember also external reliable reset is essential in real projects.

[Altera_Forum]

The problem of internal reset controllers or "self-reset" has been previously discussed. My conclusion is that you can generate a synchronously released reset signal by an internal reset generator with sufficient metastability MTBF. I'm using the method in a number of production designs where the hardware guys didn't provide a hardware reset signal.  

 http://www.alteraforum.com/forum/showthread.php?t=6067 http://www.alteraforum.com/forum/showthread.php?t=6621 http://www.alteraforum.com/forum/showthread.php?t=18591  The essential point in the metastability analysis is (if I remember the previous discussion right) that possible metastable events (= POR release violating clock setup/hold requirements) in the reset counter can't occur for all counter bits simultaneously, so you can caculate with multi-register MTBF.

[Altera_Forum]

--- Quote Start ---    I'm using the method in a number of production designs where the hardware guys didn't provide a hardware reset signal.    --- Quote End ---    Sorry to hear you have some hardware guys around you who are really hard and unhelpful. I myself have used internal reset instead of external one and it worked most but not every time. We assumed if the design didn't start well then the customer will instinctively power up again or give it a shake.  The power up reset was even regular reset whenever certain errors flagged that will force the counter back to zero. This also prevented compiler from optimising off the reset counter thinking that the programmer didn't really mean it.

[Altera_Forum]

--- Quote Start ---  the counter can power up to 0 upon configuration. is there a reason that won't work?  --- Quote End ---    Hi,  Can you please tell me how to initialize it to zero upon configuration?  Thanks, Boris.

[Altera_Forum]

--- Quote Start ---  Hi,  Can you please tell me how to initialize it to zero upon configuration?  Thanks, Boris.  --- Quote End ---    signal count: integer range 0 to 31 := 0; -- or uncheck [don't care power up] in settings  clocked process... ... if count < 31 then  count <= count + 1; end if; ...  reset <= '1' when count < 31 else '0';  or something like that

[Altera_Forum]

--- Quote Start ---  signal count: integer range 0 to 31 := 0; -- or uncheck [don't care power up] in settings  clocked process... ... if count < 31 then  count <= count + 1; end if; ...  reset <= '1' when count < 31 else '0';  or something like that  --- Quote End ---     1. I thought that initiating a signal with a logical value upon declaration has no meaning... Am I correct? 2. In settings, do you mean in Quartus?  Thanks, Boris.

[Altera_Forum]

--- Quote Start ---  1. I thought that initiating a signal with a logical value upon declaration has no meaning... Am I correct? 2. In settings, do you mean in Quartus?  Thanks, Boris.  --- Quote End ---    Modern synthesis tools are more polite and respect initial value for power up. Yes Quartus settings