Using both Stratix I and II SerDes in 10 bit @ 500 Mhz SerDes transfer. The Stratix I and Stratix II are on different Circuit Card Assemblies (CCA), the SerDes is how the CCAs transfer data. We use the SerDes to transfer single bit data and busses (time grouped data).
When the Stratix I transfers data to the Stratix II there is a lane allignment problem. We send a PRBS pattern in a lane to allign the Stratix I and II lanes per the Altera app notes. We use the lane allignement pulse to assure that the PRBS in the Stratix I transmitter is on the same lane as receiver in the Stratix II.
We see that when we transfer bussed data we get some bits from the current SerDes HighWay (HW) timeslot and some from the previous SerDes HW timeslot. While we are lane alligned, we are not lane - time alligned. This causes data failures, in that there is a time dependent protocol that is failing because we get mixed TX timeslots at the RX receivers 10-bit output. Specifcally we are transferring SerDes synchronous RMII ethernet (10-bit SerDes launch clock is 50 Mhz) and the current TX di-bits are not in the same RX slots, so the header is never decoded at the RX side.
Altera has assured us that the SerDes is a bullet proof design between Stratix I and II. We have SignalTapped and it is appears that there is an IP mismatch between Stratix I and II which will not provide time-dependent bus transfers.
Has anyone else seen this?
