CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
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I would like to see the equivalent input circuit for the Serdes clock diff inputs. Is it HSTL maybe? I only found reference to what is compatible with the input like PECL, LVDS etc.
Yes, Cyclone V receiver buffer does has internal on-chip biasing circuitry but we can't expose the internal circuit design as it's Intel proprietary design info.
However, we do have user guide doc that explained on available feature in receiver buffer. You can checkout chapter "Recevier PMA datapath" (Page 20) in below user guide link
I can see some of the IO standard that you mentioned but I don't see HSTL is a supported IO standard in the list. Pls switch to use supported IO standard as mentioned in Cyclone V datasheet.
I don't understand how your IC can take either ground referenced signals or biased signals. Do you have a blocking cap inside? I was hoping for an equivalent circuit schematic if you have one. Thanks
Yes, Cyclone V receiver buffer does has internal on-chip biasing circuitry but we can't expose the internal circuit design as it's Intel proprietary design info.
However, we do have user guide doc that explained on available feature in receiver buffer. You can checkout chapter "Recevier PMA datapath" (Page 20) in below user guide link
