Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
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Serdes Ref clk input circuit

TRoe
Beginner
785 Views

I would like to see the equivalent input circuit for the Serdes clock diff inputs. Is it HSTL maybe? I only found reference to what is compatible with the input like PECL, LVDS etc.  

This is for 5CGXFC7D6F27 part.

Thanks

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Deshi_Intel
Moderator
763 Views

Hi,


Yes, Cyclone V receiver buffer does has internal on-chip biasing circuitry but we can't expose the internal circuit design as it's Intel proprietary design info.


However, we do have user guide doc that explained on available feature in receiver buffer. You can checkout chapter "Recevier PMA datapath" (Page 20) in below user guide link


Thanks.


Regards,

dlim


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Deshi_Intel
Moderator
771 Views

HI,


You can refer to Cyclone V datasheet (table 21, page 25) for the supported IO standard for transceiver refclk pin.


I can see some of the IO standard that you mentioned but I don't see HSTL is a supported IO standard in the list. Pls switch to use supported IO standard as mentioned in Cyclone V datasheet.


Thanks.


Regards,

dlim


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TRoe
Beginner
766 Views

Deshi,

I don't understand how your IC can take either ground referenced signals or biased signals. Do you have a blocking cap inside? I was hoping for an equivalent circuit schematic if you have one. Thanks

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Deshi_Intel
Moderator
764 Views

Hi,


Yes, Cyclone V receiver buffer does has internal on-chip biasing circuitry but we can't expose the internal circuit design as it's Intel proprietary design info.


However, we do have user guide doc that explained on available feature in receiver buffer. You can checkout chapter "Recevier PMA datapath" (Page 20) in below user guide link


Thanks.


Regards,

dlim


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TRoe
Beginner
757 Views

Ok I got it Thanks! I marked it done.

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