Setting up PLL for the DDR Controller Megacore

[Altera_Forum]

Hey there ! 

 I have some trouble getting the DDR Controller to work on the Nios Development Board, Cyclone II edition. I am using Quartus II 8.0 SP1, Web Edition.  I've started my experiments from the "small" reference design, which doesn't include the controller.  The "default" reference design fails for me, and I wasn't able to get it to synthetise without errors.  I'm trying to follow the instructions given by the DDR Controller User Guide, Appendix B. Adding the component to the SOPC system was rather easy, providing the system clock is greater than 77Mhz (I've settled for 80Mhz). This my first question : do I have to clock my system at 80 Mhz, or can I keep the 50Mhz default setting, and have a PLL with x2 multiplier provide a 100Mhz clock to the DDR Controller ?  Now i have trouble with correctly setting up the pll. The documentation says I should instanciate the generated ddr_pll_cycloneii.vhd at top level, then somehow connects it to the controller.   My understanding of it is that the PLL instanciation cannot take place in SOPC builder, since doing it there ends up in configuring c0 and c1 manually, and I haven't found a way to provide the two required clock inputs to the controller.  I tried to add the ddr_pll_cycloneii.vhd file to the Quartus project using the settings > file configuration dialog. The component then shows up in the files and in the design units panel, but doesn't show up in the hierarchy panel. At that point I'm stuck, so this my second question : how do I connect the provided PLL to the DDR Controller ?  Now there is a chance I misunderstood what was required. What drove me to these conclusions was the error message that quartus give me at the classic timing analysis compilation stage. Here is the log for reference and forum searches : Error: Post compile timing analysis failed (retcode=1) Error: Output clocks to SDRAM Not Found Error: Output clocks to SDRAM Not Found Error: In-System timing verification of DDR/DDR2-SDRAM Megacore variation 'ddr_sdram_0' could not be completed due to the above errors. Error: Evaluation of Tcl script auto_verify_ddr_timing.tcl unsuccessful Error: Quartus II Shell was unsuccessful. 5 errors, 0 warnings  Error: Peak virtual memory: 55 megabytes  Error: Processing ended: Tue Nov 11 13:44:10 2008  Error: Elapsed time: 00:00:08  Error: Total CPU time (on all processors): 00:00:00  

[Altera_Forum]

--- Quote Start ---  Hey there !  I have some trouble getting the DDR Controller to work on the Nios Development Board, Cyclone II edition. I am using Quartus II 8.0 SP1, Web Edition.  I've started my experiments from the "small" reference design, which doesn't include the controller.  The "default" reference design fails for me, and I wasn't able to get it to synthetise without errors.  I'm trying to follow the instructions given by the DDR Controller User Guide, Appendix B. Adding the component to the SOPC system was rather easy, providing the system clock is greater than 77Mhz (I've settled for 80Mhz). This my first question : do I have to clock my system at 80 Mhz, or can I keep the 50Mhz default setting, and have a PLL with x2 multiplier provide a 100Mhz clock to the DDR Controller ?  Now i have trouble with correctly setting up the pll. The documentation says I should instanciate the generated ddr_pll_cycloneii.vhd at top level, then somehow connects it to the controller.   My understanding of it is that the PLL instanciation cannot take place in SOPC builder, since doing it there ends up in configuring c0 and c1 manually, and I haven't found a way to provide the two required clock inputs to the controller.  I tried to add the ddr_pll_cycloneii.vhd file to the Quartus project using the settings > file configuration dialog. The component then shows up in the files and in the design units panel, but doesn't show up in the hierarchy panel. At that point I'm stuck, so this my second question : how do I connect the provided PLL to the DDR Controller ?  Now there is a chance I misunderstood what was required. What drove me to these conclusions was the error message that quartus give me at the classic timing analysis compilation stage. Here is the log for reference and forum searches : Error: Post compile timing analysis failed (retcode=1) Error: Output clocks to SDRAM Not Found Error: Output clocks to SDRAM Not Found Error: In-System timing verification of DDR/DDR2-SDRAM Megacore variation 'ddr_sdram_0' could not be completed due to the above errors. Error: Evaluation of Tcl script auto_verify_ddr_timing.tcl unsuccessful Error: Quartus II Shell was unsuccessful. 5 errors, 0 warnings  Error: Peak virtual memory: 55 megabytes  Error: Processing ended: Tue Nov 11 13:44:10 2008  Error: Elapsed time: 00:00:08  Error: Total CPU time (on all processors): 00:00:00    --- Quote End ---    Hi,  I used a DDR controller long time ago and I remember that the megawizard generates some TCL scripts (e.g. one for the timing analysis). These files must be in the Quartus rundir. Otherwise they will fail. I will look for the old project, maybe I found a more detailed answer.

[Altera_Forum]

After upgrading to Quartus 10.1 I am getting this error, did you find a solution? 

Thanks, Richard

[Altera_Forum]

I'm also getting that error after upgrading to 10.1. 

 Did you find a solution? :p

[Altera_Forum]

I found a work-around probably frowned upon. I just comment out the reference to the tcl script in the qsf file.

[Altera_Forum]

I found a hack to fix this, but I am not sure if I did the right thing. I have Quartus II 10.1 installed under C:\altera\10_1\ So all paths here refer to that base directory. I patched the file C:\altera\10_1\ip\altera\ddr_ddr2_sdram\lib\tcl\paths.tcl In the procedure "extract_clk_tco" there are the lines 

  } elseif { $family == "cycloneii" } { ::ddr::extract::follow_edge2 mux async "${basename}\\|ddio_out_...:auto_generated\\|muxa\\\\\\]\$" found_tco "" failflag ::ddr::extract::follow_edge2 mux async "~DELAY_CELL\$" found_tco "" failflag } elseif { $family == "stratixii" } { I think the 2nd "::ddr::extract::follow_edge2 mux ..." is wrong so I changed that to    } elseif { $family == "cycloneii" } { ::ddr::extract::follow_edge2 mux async "${basename}\\|ddio_out_...:auto_generated\\|muxa\\\\\\]\$" found_tco "" failflag# ::ddr::extract::follow_edge2 mux async "~DELAY_CELL\$" found_tco "" failflag } elseif { $family == "stratixii" } { commenting this line out. After that it worked without problems. so long