SignalTap different sample depth led to different logic

[Altera_Forum]

Hi guys, 

 I met a problem recently. I am using signaltap to capture some signals. When the sample depth is 2k, the signals are correct. But when I change the depth to 4k, some of the signals become weird. For example: a register changed all the time when it should stay unchanged.   I am using Quartus ii 14.1 and Cyclone 5.  Does anyone know what's going on?  Thank you.  Leon

[Altera_Forum]

Does your design meet timing? 'Simply' doubling the RAM size may have ramifications on fit and timing. Make sure it meets timing. 

 Cheers, Alex

[Altera_Forum]

--- Quote Start ---  Does your design meet timing? 'Simply' doubling the RAM size may have ramifications on fit and timing. Make sure it meets timing.  Cheers, Alex  --- Quote End ---   Thank you Alex.  I only have some unconstrained paths: +---------------------------------------------------+ ; Unconstrained Paths ; +-------------------------------------+-------+-------+ ; Property ; Setup ; Hold ; +-------------------------------------+-------+-------+ ; Illegal Clocks ; 0 ; 0 ; ; Unconstrained Clocks ; 2 ; 2 ; ; Unconstrained Input Ports ; 3 ; 3 ; ; Unconstrained Input Port Paths ; 188 ; 188 ; ; Unconstrained Output Ports ; 33 ; 33 ; ; Unconstrained Output Port Paths ; 16901 ; 16901 ; +---------------------------------+-------+-------+  Could this be the problem?  Thank you.  Leon

[Altera_Forum]

it depends if they are critical to the design you are checking. 

Do you also have some asynchronous paths into the logic? Did you check that the design met timing?

[Altera_Forum]

--- Quote Start ---  it depends if they are critical to the design you are checking. Do you also have some asynchronous paths into the logic? Did you check that the design met timing?  --- Quote End ---    Hi Tricky,  Yes I have asynchronous paths in the logic.  The timing is OK since the TimeQuest Timing Analysis is green and nike after compile design. The only timing related issues are some Unconstrained Paths shown above.  Thank you!  Leon

[Altera_Forum]

You should definitely at least constrain all clocks. Just because you don't see a timing failure doesn't mean anything unless the design is fully constrained.

[Altera_Forum]

Asynchronous paths are also an issue. They will not be timed, and their path delay will vary from build to build and with temperature.  

 Make sure everything is synchronised and everything is constrained.

[Altera_Forum]

Thank you guys. The problem is solved after adding some timing constraints to the clocks lol. 

 Leon