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Simple Avlalon master: memory filler

Altera_Forum
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This example is to address a couple people who asked if anyone had an example Avalon master peripheral. This peripheral has an Avalon master & Avalon slave port; the slave port is used for control, and the Master for writing blocks of memory. The peripheral is written in Verilog. The peripheral takes commands on the slave port to fill a section of memory; register writes to the slave to define pattern to write, start address, and# of words to write, and control are used to start the operation. The memory filler does the rest. In testing, this peripheral can write to SDRAM at one clock per word (aside from a few setup clocks to get things going and the occasional bank switch or refresh). 

 

The peripheral could be easily modified to read -- just add a read output and readdata input to the Avalon master in Verilog + class.ptf, and add appropriate control logic to use the readdata as you see fit. 

 

To use this in a system, unzip the zip file into a suitable directory - make sure that a new subdir is created called "memory_filler". Then, open SOPC Builder and in the Setup menu, add the path to your directory. Alternatively, just unzip the file into altera/kits/nios2/components/memory_filler. The peripheral should then show up as a 'green dot' under the "Avalon Modules" folder. 

 

There is a word doc which explains how to use it from the legacy SDK (simulation & GERMS mon) - the register set is pretty easy and one could easily run/simulate from the HAL environment as well (you'll need to write a header file to define the register offsets; the Nios II SW dev docs should describe this). 

 

No warranty or support expressed or implied. Not an Altera product.
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Altera_Forum
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--- Quote Start ---  

originally posted by jesse@Oct 14 2004, 11:37 AM 

this example is to address a couple people who asked if anyone had an example avalon master peripheral. this peripheral has an avalon master & avalon slave port; the slave port is used for control, and the master for writing blocks of memory. the peripheral is written in verilog. the peripheral takes commands on the slave port to fill a section of memory; register writes to the slave to define pattern to write, start address, and# of words to write, and control are used to start the operation. the memory filler does the rest. in testing, this peripheral can write to sdram at one clock per word (aside from a few setup clocks to get things going and the occasional bank switch or refresh). 

 

the peripheral  could be easily modified to read -- just add a read output and readdata input to the avalon master in verilog + class.ptf, and add appropriate control logic to use the readdata as you see fit. 

 

to use this in a system, unzip the zip file into a suitable directory - make sure that a new subdir is created called "memory_filler". then, open sopc builder and in the setup menu, add the path to your directory. alternatively, just unzip the file into altera/kits/nios2/components/memory_filler. the peripheral should then show up as a 'green dot' under the "avalon modules" folder. 

 

there is a word doc which explains how to use it from the legacy sdk (simulation & germs mon) - the register set is pretty easy and one could easily run/simulate from the hal environment as well (you'll need to write a header file to define the register offsets; the nios ii sw dev docs should describe this). 

 

no warranty or support expressed or implied. not an altera product. 

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The link does not work. Could you post .zip file again please ? 

Thx.
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Altera_Forum
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Right now (28-Nov-2006), the link works.

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