Simulation error when simulating PLL

[Altera_Forum]

Hello, 

 I am using run time configurable PLL in my project containing Arria V FPGA. I need to vary the output frequency of the PLL at run time. I have written a logic for loading the N and M counters. However when I simulate using modelsim, I get the following error:  "Time: 0 ns Iteration: 0 Protected: /test_bench/dut/pll1_inst/pll_1_altera_pll_altera_pll_i_586/<protected>/<protected>/<protected> File: nofile# FATAL ERROR while loading design"  I googled this out and found out confessions from Altera in the following website :  https://www.altera.com/support/support-resources/knowledge-base/solutions/rd08182013_307.html  I couldnt get much of what is explained there. Is it mentioning that I need to migrate my design from VHDL to verilog? I am not using .do file or .tcl file. Is there a work around for simulating without using these files? Please help.

[Altera_Forum]

Referring to the link you provided, you can issue (type) that 'vlog' command in ModelSim's Transcript window without needing to add it to a tcl script. However, the advantages of having your simulation captured in a tcl script are worth considering... 

 ModelSim requires the functional behaviour of the PLL. The support solution is simply pointing out that it can obtain these from either the vhdl or verilog libraries that come with Quartus. However, there is clearly an issue with ModelSim and compiling the vhdl libraries. Hence, the solution's suggestion to use the verilog libraries.  Cheers, Alex