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Honored Contributor I
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Simulation of PLL lock time

The lock time for my PLL is far different than what I see in simulation, does anyone know why?

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Honored Contributor I
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Since the PLL is an analog circuit, lock time varies based on PVT, PLL bandwidth, etc. There is no way to exactly predict the lock time of a PLL. Therefore, the Quartus simulator just waits x number of cycles and just says your PLL is locked. This makes sense since most of the time you're concerned with simulating what happens in your logic after your PLL has locked.

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