Single-Ended I/O Performance on MAX10

[akohlsmith]

The "High Speed I/O Specifications" section of the MAX10 datasheet says to refer to the package-specific pinout file for specific I/O performance.

However, the pinout files have a revision in December 2016 which states that the performance specifications for single-ended I/O was removed. No other information is available.

How do I find out what "High speed" and "Low speed" I/O means for single-ended signals on a 10M25DA in a the 256-ball package and C8 speed grade?

[SreekumarR_G_Intel]

Hello Andrew , https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/max-10/ug_m10_gpio.pdf In the above link reference to the section 2.2.2, only mentioned about location of the high speed and low speed IO refer pinout document , For the performance can you kindly refer the below link https://www.intel.com/content/www/us/en/programmable/documentation/mcn1397700832153.html#mcn1398043804031 Can you let me know if you have any other questions /concern related to same ? Thank you , Regards, Sree

[akohlsmith]

Hello Sree,

I don't think that you answered my question. You are correct that the maximum data rate for *differential* I/O standards is well-documented. I am asking about the maximum data rate for *single-ended* I/O standards. I cannot, for instance, find how fast a "Low Speed" I/O pin can toggle when operating as a 3.3V LVCMOS I/O standard on a M1025DAF256C8.

The datasheet says that this information is in the pinout file, but the changelog in the pinout file says that this information was removed in December 2016.

Where can I find the I/O toggle rates for single-ended I/O standards?

Thank you,

Andrew

[GLees · Accepted solution]

The answer to your question is that Altera/Intel no longer supplies single-ended toggle rate information. They tell you to do an IBIS simulation. This is very frustrating when all you typically want to know is whether "low speed" means 100Mhz, 10Mhz or 1Mhz.

[akohlsmith]

Yes, that is exactly where I'm coming from! I would like a general idea, not an exact number. Can I/O in bank 8 at 3.3V LVCMOS handle 125MHz DDR? I am suspecting that the single-ended numbers are poor which is why they stopped publishing them. Does anyone happen to have the 10M25DAF256 pinout documents from before December 2016? This is so frustrating.