Soc/HPS based on DE10-Nano : how do I program a DPR and/or UART

[Altera_Forum]

Hello everyone, 

I am in a process of porting my application from a MAX10/DE10-Lite/NIOSII environment  (https://github.com/pdp11gy/dec-rl02-rl01-disk-emulator) to an SoC/HPC environment  based on the DE10-Nano board. At first I worked successfully with the DE0 Nano-SoC  board, but it did broke and I had to get the replacement board , DE10-Nano. And again, here is a lot different. My main problem is in the I / O area. The PIO's are working fine, but i have Problems with the Dual-Ported-Ram(DPR) and with an additional UART. I am NOT able to copy data to and from the DPR via memcpy  In a NIOSII environment , it did work fine like this example:# define DPRAM_BASE 0x00100000 // Base-Address DPR# define DPRAM DPRAM_BASE  memcpy((void *)(DPRAM), &RLDRIVE.rl_drive_i[0], 11520);  In the SoC/HPC environment. int fd; // Hold FPGA address void *virtual_base; // Virtual addr that maps to physical void *DPR_addr; // Dual Ported Ram address . DPR_addr = virtual_base + ( ( unsigned long )( ALT_LWFPGASLVS_OFST + DPR_BASE )  & ( unsigned long)( HW_REGS_MASK ) );  I did try the memcpy as following: memcpy((void *)(DPR_addr), &RLDRIVE.rl_drive_i[0], 11520); // Not working  memcpy((void *)(uint32_t *)DPR_addr, &RLDRIVE.rl_drive_i[0], 11520); // Not working .... and a lot of more tries.....but without success Enclosed , please find the complete test c-programm.  Also, I am not able to load my .rbf file using de10_nano_linux. The following script did work fine with the DE0-Nano-SoC unix but on the de10_nano_linux , I miss the Pass /sys/class/fpga-bridge/fpga2hps/enable ....# !/bin/sh echo 0 > /sys/class/fpga-bridge/fpga2hps/enable echo 0 > /sys/class/fpga-bridge/hps2fpga/enable echo 0 > /sys/class/fpga-bridge/lwhps2fpga/enable dd if=RL_EMULATOR.rbf of=/dev/fpga0 bs=1M echo 1 > /sys/class/fpga-bridge/fpga2hps/enable echo 1 > /sys/class/fpga-bridge/hps2fpga/enable echo 1 > /sys/class/fpga-bridge/lwhps2fpga/enable My workaround is, to generate a .jic file and use the EPCS mode. I hope it has no influence  Any hint is welcome and many thanks in advance, Reinhard

[Altera_Forum]

I found the problem by myself, I did not care about the axi_master which is necessary for a dual_ported_RAM. Code has to be changed: 

# define ALT_AXI_FPGASLVS_OFST (0xC0000000) // axi_master # define HW_FPGA_AXI_SPAN (0x40000000) // Bridge span # define HW_FPGA_AXI_MASK ( HW_FPGA_AXI_SPAN - 1 ) // void *axi_virtual_base; axi_virtual_base = mmap( NULL, HW_FPGA_AXI_SPAN, ( PROT_READ | PROT_WRITE ), MAP_SHARED, fd,ALT_AXI_FPGASLVS_OFST );  // DPR_addr = axi_virtual_base + ( ( unsigned long )( DPR_BASE )); // -> Now, also the memcpy works, see my example: memcpy((void *)(DPR_addr), &RLDRIVE.rl_drive_i[0], 11520); // RAM => DPR memcpy(&RLDRIVE.rl_drive_i[0], (void *)(DPR_addr), 11520); // RAM <= DPR  ...  I still have the problem, that I can't load my .rbf file