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Sopc2dts "Transparent bridge not yet supported" meaning?

Honored Contributor II

Hi folks, 


I am trying to make SoC System based on this tutorial ( What I know have done is connecting two Altero FIFOs to the FPGA to HPS AXI bus of the HPS (see attachment for a screenshot of the upcoming sentences). These FIFO's are also the bridge between two different clock domains (and therefore are clocked by two different clock signals). Furthermore the FIFOs have four Avalon memory mapped interfaces: In, Out, CSR (control status register) in, and CSR out. The Out and CSR out Avalon interfaces of the FIFOs are directly connected to the FPGA to HPS AXI interface of the HPS. No other devices are connected to this port. 


If I try to generate the Device Tree Source, via the following command 

sopc2dts --input soc_system.sopcinfo --output soc_system.dts --type dts --board soc_system_board_info.xml --board hps_common_board_info.xml --bridge-removal all --clocks  


I get the errors/warnings: 

Transparent bridge in fifo_57_0 of type altera_avalon_fifo is not yet supported. Transparent bridge in fifo_65_0 of type altera_avalon_fifo is not yet supported. 


Unfortunately I cannot find any information about those errors/warnings on the web. Could anybody provide me (with a link to) more information about these messages? 


Edit: I found this: Is those messages part of the "Spurious Error Messages from sopc2dts"? 


P.S: Could this problem possibly be solved by adding a pipeline MM bridge between the HPS and FIFOs? Than the connection is not "transparent" anymore.
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Honored Contributor II

Hi guys, 


I found my solution! I Assumed that my Custom IP and a PLL in my Qsys design didn't end-up in the DTS due to this messages. However I realized this morning that this is the case due to that the HPS is not connected to my custom IP and the PLL xD According to, you could savely ignore this message, so I am going to do that!