Stratix 10 PCIe Configuration Register Access

Programmable Devices

CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers

Stratix 10 PCIe Configuration Register Access

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Hi everyone - I have an Arria 10 PCIe design that I am starting to look at migrating to Stratix 10 but have hit a problem as the Local Management Interface has been removed. In the Arria version, I use the LMI to read the BAR0 and 4 base addresses so I can work out offset addresses of TLPs during run-time. As the Stratix version of the Avalon-ST PCIe core does not have the LMI, I can't seem to work out how to get access to the configuration space to read these values (or, for that matter, any other configuration value that Altera hasn't put on the Transaction Layer Configuration Interface).

Does anyone have any ideas how to work around this? Am I just spectacularly missing something with the new device?

Thanks,

Andy

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