Stratix 10 PHYLite avalon bus avl_readdata seems to be synthesized away

[LHinC1]

Hi Altera AE ,

    We are working on a design on Stratix 10 using PHYLite library.

    We previously use Arria 10 PHYLite in our last project, it was smooth and we didn't encounter any problem in Arria 10.

    In Stratix 10, the waitrequest signal was stuck at high all the time

    before we issue any command to the avalon bus after reset.

    We solved this by issuing a number of dummy write commands to avalon bus, the waitrequest signal returns to 0.

    We got help from Altera AE on this issue, and now we see another issue thus I raise a post here.

    After solving the waitrequest issue, we continue to read the basic information from the avalon bus,

    we can see the readdata_valid pulse in signal tap but avl_readdata is always 0

    when we read the address 0x05000024.

    We don't see anything wrong in the RTL, but we see that the avl_readdata is always 0.

    Until we make an irrelevant change to the code, the avl_readdata becomes normal again such that the readdata_valid looks the same as what it is when the avl_readdata is 0.

    It is so weird, we spent a couple of days on this.

    Please help us on this, we have been stuck on the avalon bus communication for 3 months.

    FYI : we are using quartus version 19.3

Thanks,

Samson

[Rashmi1]

Hi Samson,

The quartus version 18.1 document is the latest. New version is not yet published yet.

Engineering is still debugging your issue. I havent heard back anything yet.

Thanks,

Rashmi

[LHinC1]

Hi Rashmi,

We are doing simulation on the PHY Lite in ModelSim-Intel on v19.3 and v20.2. We see the data is 0xffffffff when we read a corresponding address on the PHY Lite.

We followed the instructions on AN888, on page 16 - 17, it says: "From the Intel Quartus Prime Pro Edition software, click Processing > Start Compilation to compile the reference design."

And then the next part is Hardware Testing section.

Is there any more information on the steps to perform a post-compilation simulation on the PHY Lite?

Thanks,
Samson

[LHinC1]

Hello Rashmi,

We compiled the design using Quartus Prime v20.2, the result is the same.

I have attached the picture from Signal Tap and I attached our project archive.

Thanks,

Samson

[Rashmi1]

Hi Samson, 

Can you please confirm on the below questions: 

Customer design: 
Interface frequency is 1200MHz, Quarter clock rate, LVDS with on-chip termination, SSTL-12
1st Phylite instance: output DDR, 4 groups and different pins per each group
2nd Phylite instance: output DDR, 1 group and 4pins
3rd Phylite instance: output DDR, 4 groups with different pins per each group
4th Phylite instance: output DDR, 3 groups with 9 pins per each group 
5th,6th,7th Phylite instances: output DDR, 2 groups with 9 pins per each group

1. You are using the PHYlite interface to DDR4, they write their own code in Avalon-mm debug in order to process the calibration? 
2. To understand the design background, is the customer using all the Phylite groups to communicate with a DDR4 by using a multiple of cables to connect them? 
3. How are you trying to use a new version of Quartus, still can see the identical issue? Did you try to instantiate other IO bank location instead of Bank 3 (Bank 3B, 3K, 3L, 3J, 3I, 3D and 3C)? 
4. Instead of 1200MHz interface frequency, did you reduce the interface frequency? If yes, did you face the same issue, and please share the result.

5. I proposed you to  uses a new Quartus and pending your update for this, If this is the root cause, it will be fixed in Quartus 20.1. 

6. If you got chance to simulate your design can you  share the simulation result of this? 

Thanks,

Rashmi 

[Rashmi1]

Hi Samson, 

Can you please confirm on the below questions: 

Customer design: 

Interface frequency is 1200MHz, Quarter clock rate, LVDS with on-chip termination, SSTL-12

1st Phylite instance: output DDR, 4 groups and different pins per each group

2nd Phylite instance: output DDR, 1 group and 4pins

3rd Phylite instance: output DDR, 4 groups with different pins per each group

4th Phylite instance: output DDR, 3 groups with 9 pins per each group 

5th,6th,7th Phylite instances: output DDR, 2 groups with 9 pins per each group

1. You are using the PHYlite interface to DDR4, they write their own code in Avalon-mm debug in order to process the calibration? 

2. To understand the design background, is the customer using all the Phylite groups to communicate with a DDR4 by using a multiple of cables to connect them? 

3. How are you trying to use a new version of Quartus, still can see the identical issue? Did you try to instantiate other IO bank location instead of Bank 3 (Bank 3B, 3K, 3L, 3J, 3I, 3D and 3C)? 

4. Instead of 1200MHz interface frequency, did you reduce the interface frequency? If yes, did you face the same issue, and please share the result.

5. I proposed you to uses a new Quartus and pending your update for this, If this is the root cause, it will be fixed in Quartus 20.1. 

6. If you got chance to simulate your design can you share the simulation result of this? 

Thanks,

Rashmi 

[LHinC1]

Hello Rashmi,

1. Yes, we are using the PHYlite interface to DDR4; correct, we process the calibration by ourselves. We used Arria 10 in our last project, we used PHY Lite on Arria 10 as well, we just don't know why it is so weird on Stratix 10.

2. We use test socket to interface the DDR4.

3. Yes, we see the same issue using v20.2, we have finished our PCB design, the IO pins are all populated in Bank 3.

4. It is not related to the speed, we are running 1600Mbps, we are trying to communicate with the PHY Lite on the avalon bus, but we failed to read the basic information from the PHY Lite on the addresss 0x05000024.

5. We are currently using v20.2.

6. We did the simulation on ModelSim-Intel, the waitrequest and valid signals are correct, but the readdata is 0.

Thanks,

Samson

[LHinC1]

Hello Rashmi,

I have discussed with my team, we hope to get a simple reference design which has a correct response on the avalon bus with the PHY Lite, and then we may modify our design on that and we may see the RTL to check what is wrong with our logic.

We received a simple example from Altera FAE Nur Aida before, today I modified this example to read the address 0x05000024 on our test board, but the data is still 0.

I have attached the archive project here, this is a very simple design, would you please help us to take a look on it? There is a signal tap file called "aida_file_v2.stp", would you please help to take a look to see if there is anything wrong?

The PHY Lite is very important to us, we have been stuck on this of a couple of months.

Thanks,

Samson

[Rashmi1]

Hi Samson,

1. How did you get the address, 0x05000024?
2. Did you reset the board after the issue happens? For example, reset the board and power on, run the design then issue occurs, reset the board and run again. 

Thanks,

Rashmi

[LHinC1]

Hello Rashmi,

1. 0x05000024 is the base address on the PHY Lite.

2. The issue happened on the very first time when we turn on the FPGA power, and it is never normal after power up nor we do the reset.

3. We have found a way to write a state machine to communicate with the PHY Lite. We do this as a patch, hope this would give you some hints on this issue. I have attached my FSM code here. Please that we added 2 dummy states : SEARCH_INTERFACE_TABLE_0 and SEARCH_INTERFACE_TABLE_VALID_0 to make it work.

Thanks,

Samson

[LHinC1]

Hello Rashmi,

Excuse me, is there any update?

Thanks,

Samson

[Rashmi1]

Just to double confirm, the original design is A10, are you directly migrating this design from A10 to S10 without changing the RTL? The only change you have made is the pin assignments on S10 ?

[LHinC1]

Hello Rashmi,

Thank you for your support.

Our last project was on Arria 10, when we migrate to Stratix 10, I regenerated the PHY Lite library code in Quartus 19.3 / 20.2 (as the library of Arria 10 is not compatible with Stratix 10 device).

And then I connected the PHY Lite in Stratix 10 in the same way as we did on Arria 10.

Regarding "without changing the RTL", for the logic outside the PHY Lite, I think we didn't make any RTL changes.

Thanks,

Samson