Stratix 10 hold time doubt, low resource occupation FPGA

[Swift8051]

Hi everybody,

I have a curiosity/information related to Intel / Altera FPGAs (eg Stratix 10).
A collegue of mine stated that if the FPGA is almost empty as for FW resource occupation, there can be, more easily, violations on the hold times of the internal FF.

The person who supported this possibility said that, Stratix 10 family, for instance, is designed to give the maximum (as for meeting timing) with a consistent occupation of resources and, if this is missing, the internal paths suffer with possible violations of the Thold.
He said that this is due to the fact that the logic, when the FPGA is almost empty, has difficulty in keeping the data stable with respect to the clock, with consequent violation of the Thold.

I had never heard such a thing so I'd like to ask for information or denial about it.

Thank you very much,

[sstrell · Accepted solution]

I've never heard of such a thing either.

Hold time violations occur because of "too fast" signaling, causing signals to not be held long enough after a long edge.  A mostly empty device gives the Fitter basically an infinite number of possibilities for placing and routing a small design that will meet timing as long as correct timing constraints are created.  The Fitter will follow the constraints to meet timing, not just put stuff close together because it can.

[Swift8051]

Thank you for your reply sstrell,

it seemed very strange infact... thank you for confirming.