Stratix-3 to Pic18F4550

[Altera_Forum]

Hi all,  

 I'd like some suggestions to a potential design I'm writing up.  I have a the stratix-3 dsp devel kit, it contains the stratix-3 devel board plus an ADC/DAC board connected via one of the hsmc connectors.   I take some data on the adc and process it on the fpga (matched filter). At the end of it all, I have 64 bits that I would like to get off the board every 20ms. Not a big deal right? At such a low data rate, I shouldn't have any questions .....  But I need to offload the data to a pic, (pic18f4550). I know this isn't a pic forum, but for those interested, I was going to use the streaming parallel interface on the PIC for this job. The PIC will then send out the data via 802.11.  Now, the stratix is operating at 3.3LVTTL. All my calculations show that I should NOT need level converters to talk to the 5V pic, with the exception of the read/write pin that is asserted by the pic. For that situation, I'll just use a pull up transistor to convert the 5V to 3.3V. Otherwise, my data lines from the FPGA(3.3V) should satisfy the requirements for 5V TTL input operation. Does this sound legit?  Thanks  Matt

[Altera_Forum]

For the FPGA-to-PIC signals, 3.3V -> 5V does not need any level translators. 

 You'll need to make sure that you do not enable any pull-up on the PIC input, as that would pull-up to 5V. When your FPGA is not configured those pull-ups can forward bias the FPGA I/O diodes.  You can always play it safe and add some series resistance between your FPGA and PIC signals. That way if the PIC comes on with 5V levels on its I/Os, and the FPGA is still configuring, you'll limit the current to safe levels.  If you have any PIC signals going back to the FPGA, then you need to take care not to violate the input voltage maximum of the FPGA I/Os. If you're only doing this on a couple of signals, you can use a voltage divider.  Cheers, Dave