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Stratix II clock signal generation

Altera_Forum
Honored Contributor II
‎01-13-2009 01:18 AM
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Hi All. 

 

I have just started on FPGA's , and am still getting to grips with VHDL. I have a task in which involves the usage of a Stratix II FPGA to generate a variety of clock signals. 

 

Would someone be able to give me some information on how to do this. 

 

It would be greatly apprecated, 

 

Aoedogg.
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Altera_Forum
Honored Contributor II
‎01-13-2009 09:33 AM
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I suggest you start with the Alter PLL user guide 

http://www.altera.com/literature/ug/ug_altpll.pdf
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