An easy way to check these types of things is to use the Quartus II Pin Planner feature. This new feature lets you look at all kinds of things related to your pins. It's especially useful for exactly these types of questions. It shows a graphical representation of all the pins and their functions.The easiest way I found to do this is to go to the Pin Finder (binoculars button in pin planner) and set up a query for I/O standard = LVDS. The query quickly returns the number of pins per bank that meet your criteria. In this case you should divide the number returned by 2 to get the number of LVDS channels.
You can have LVDS inputs on the dedicated clock pins, but they don't have the SERDES circuitry that the side banks have.There are a total of 4 dedicated input clock pin pairs on top banks and a total of 4 dedicated clock pin pairs on the bottom banks. The top and bottom banks can't support LVDS toggle rates as high as what the side I/O banks can support, and they don’t have differential termination resistors. They are useful for getting differential clocks to the enhanced PLLs.