Hi,
I'm a little confused about the IO timing on an EP3SL340 speed grade C4. If I'm reading this correctly, the column I/O timing has a setup and hold requirement of (-2.890, 3.434) and the row has a (1.786, -1.263) with 3.3V LVTTTL with the clock sourced by a GCLK pin and a PLL. The row timing is pretty much what I expected but the column timing values are quite different. Does this mean the data must be stable from 2.890 to 3.434 ns after the rising edge of the clock?
If that's the case, how does anyone a synchronous data transfer using a column pin without playing clock phasing games?
Also the Tco times seem to be really large when a PLL is being used. Is there a very large delay in the global clocking to the columns? I couldn't fine a mention of it in the clock networks section of the databook.
If anyone could point me to the correct sections of the databook, I would appreciate it.
Thanks
CNN version: Is the column IO timing (Tco, Tsu, Th) radically different than row timing IO?
