Stratix III reconfigurable PLL switched clocks

[Altera_Forum]

Hello! 

 I'm having some strange troubles with a reconfigurable PLL. I have to write my settings to c2 to configure c1 and vice versa.  The baseclock is 5.25MHz. The M multiplier is 199 (100 high count / 99 low count). 5.25*199= 1044.75MHz.  Now I want c0 to be 104.475 MHz, c1 also 104.475 MHz (with 90° phase shift) and c2 double frequency 208.95 MHz.  This translates in following high/low counts: - c0 5/5 (1044.75/10=104.475) - c1 5/5 (1044.75/10=104.475) - c2 3/2 (1044.75/5=208.95)  If I write these settings to the PLL, my project don't work. With SignalTap, I discovered that the clocks c1 and c2 coming out of altpll_component are switched. c0 and c2 have the same frequency and c1 has the double frequency.  After triple checking, the code, settings and stuff, I tried switching the settings: - c1 3/2 - c2 5/5  With this, my project does work! And SignalTap confirms that c0 and c1 have the same frequency and c2 has the double frequency. But I still don't know why I have to switch the settings? This can't be correct.  Writing the settings to the altpll_reconfig is pretty straightforward. I can't imagine that I do something wrong there because otherwise the pll would be totally configured wrong I think. I also double checked that I use the right settings for writing to the pll (c1 is counter_type 0101, c2 is counter_type 0110).  And because of the measurements I did with SignalTap, I can confirm that the clock signals coming out of the pll are already switched and it is not a switch further on in my code.  Do I forget something? Do I miss something?  Thanks in advance! JBC

[Altera_Forum]

Check if input clock isn't too slow.

[Altera_Forum]

Hi Socrates, 

 How could this have an influence? And how can I check this?  I would say that the input clock is not to slow, because I can get the desired frequencies (however on the wrong output). I've also kicked out the reconfig PLL and used a "non-reconfig" PLL. Everything worked just fine and I had no trouble with the frequencies (with the same input frequency; 5.25 MHz).

[Altera_Forum]

Well, check the docu. If non reconfigurable PLL work fine, then something is bad with the reconfiguration itself.

[Altera_Forum]

True but I've spend already a lot of time on recalculation, double checking and verifying the reconfiguration settings. 

 And I think they are correct because I get my needed frequencies, only I have to reconfigure c1 with the c2 settings and c2 with the c1 settings.

[Altera_Forum]

Update: 

I think it has to do something with this option:  http://quartushelp.altera.com/11.1/mergedprojects/logicops/logicops/def_preserve_pll_counter_order.htm  I'll verify and let it know...

[Altera_Forum]

Setting the option "Preserve PLL Counter Order logic" solved the problem. I must have overlooked this.

[Altera_Forum]

--- Quote Start ---  Setting the option "Preserve PLL Counter Order logic" solved the problem. I must have overlooked this.  --- Quote End ---    Hello JBC,  I am a newbie at PLL dynamic reconfiguration. I was searching the Forum and came across your message. Please, if you could give me some tips....  1. Summary of task: I have a Stratix III FPGA and want to dynamically adjust all the ouputs (C0 - C9) of the PLL1 (Top/Bottom) to the same desired frequency (for example change the clock outputs C[9:0] from 1 MHz to C[9:0] 200 MHz.) Note: These clocks are also hard coded during ALTPLL1 instance setup to have 45 degrees phase shifted from each other, example C0 = 0 degree, C1 = 45 degress, C2 = 90 degree....) I believe the formula to change the frequency is Fout = Fin x (M/(NxC); Fout = Output Frequency, Fin = Input Frequency (in this case = 10 MHz), M = feedback multiplier counter, N = pre-divider counter, C = post devidiver counter.  2. Problem: I have so far set up two instances ALTPLL_RECONFIG and ALTPLL1 using the MegaWizard_PlugIn Manager. For setting up the desired output frequency, I need to set up the counter_type[3:0] and the counter_param[2:0] and I don't quite understand what these two parameters are about and how to select them properly. There are set up for counter's high count, low count...What do they mean?  I also noticed that in the data specs for counter_type, it does not list binary code for the post divider counter C! The data specs/app notes do not say much. Can you provide some explaination....Thank you DaveN Note: In my design I am not using .mif file/external ROM to reconfigure the output clocks. The control signals/data to reconfigure the output clocks come from a state machine.

[Altera_Forum]

Hello daven, 

 Sorry for my late reply, I didn't got noticed of this reply by mail earlier.  It has been some time when I used dynamic PLL configuration, but I let you know what I know and remember.  First of all, your formula seems correct. What we did to have all correct settings for a dynamic reconfiguration was not calculating them let Quartus calculate/decide them. We scripted with tcl a tool that changed the input files with the desired frequency for all phase shifted clocks, compile the project, read the reports for the PLL settings and copied them into a table. This was done for all 300 or so frequencies we needed. Then you are sure that all settings are feasible.  The resulted table with all needed frequencies and all phase shifted clocks was then loaded into the software (CPU aside from the FPGA) that decided which frequency to use. The CPU then sends the data to the FPGA via a wrapper interface around the altpll_reconfig instance. The counter_type and counter_param is used to tell which setting from which clock you want to change, you just use the binary code from the datasheet (http://www.altera.com/literature/ug/ug_altpll_reconfig.pdf).  Hope thiss helps! Kind regards, JBC

[Altera_Forum]

Hello, 

In Stratix III FPGA, reconfigurable PLL (top/bottom PLL), I want to ensure the output clocks have low jitter. How do I go about to set up any parameter to control this? I've noticed there's a parameter call VCO counter and it has something to do with bandwidth setting that affect the output clock jitter. Is this the right parameter to look at for controlling output clock jitter? Please advise on how to control/setup the PLL's jitter for output clocks.... Thank you....Daven