Stratix V - Weak Pull Ups

[DS13]

Hi,

I want to use a Stratix V GX (P/N: 5SGXMA5K3F40C2N) in my design. 

I saw on Figure 8-1 on Stratix V Handbook (Vol. 1), on "Configuration Sequence for Stratix V Devices", that all I/Os are tied to weak pull up after POR exit until configuration is over.

1. What is the weak pull-up resistors value?

2. Is there a way to disable these weak pull-ups during this time period (after POR exit until configuration is over)?

3. In my design, I have an unpowered IC that is connected to FPGA User I/Os. This other IC is powered-on only after FPGA configuration is completed. This means that the FPGA weak pull up resistors can drive current into the other unpowered IC I/Os.

Do you have recommendations on how to deal with this situation of current drive into I/O or prevent it?

Thank you.

[AqidAyman_Intel]

Hi,

Thank you for reaching out Intel FPGA Community.

1. From the handbook, it mentioned for the pull-up resistor, typically 25 kΩ.
2. From what I understand, the weak pull-up resistor (R) in the Stratix V input/output element (IOE) is enabled during configuration download to keep the I/O pins from floating.
3. This device is supporting Hot-Socketing Implementation which means this feature tri-state the output buffer during power up and power down of the power supplies. Hot-socketing circuitry prevents excess I/O leakage during power up. Please be noted that the hot-socketing feature is not applied to the configuration pins. Therefore, these pins will drive out during power up and power down.

Regards,

Aqid