StratixIIGX and DDR2RAM interfacing issue

[Altera_Forum]

Hi All,  

 I am using StratixIIGX Dev board (stratixIIGX_2sgx90_pcie) for writing data from external off-board RAM (attached through HSMC connector) to the DDR2RAM available on Altera's StratixIIGX Development board. I am using ALTMEMPHY DDR2 RAM HPC (mega function) and Quartus II 9.1.   When I compile the program, it generates the following error messages.  error: too many output and bidirectional pins in i/o bank 7 assigned  near vref pin ar16 (vrefgroup_b7_n1) on device ep2sgx90ff1508c3 -- no more than 20 output and bidirectional pins allowed near the vref pin when voltage referenced pins are driving in, but there are potentially 21 pins driving out  Can anybody help me in this regard?  Thanking in anticipation.

[Altera_Forum]

Go to Tools -> Tcl scripts and execute a script, generated by DDR2 memory core. This will assign pins to a certain output enable group, set required current values, etc. You can do this on Your own by seting different output enable groups for certain pins in Assignment Editor.

[Altera_Forum]

Thanks Socrates for your timely reply and helping me out.  

TCL script file, generated by DDR2 memory core, works fine but with a little change in it. We need to add "Instance Name" of the DDR2 controller module. In my case it was not there previously.