Well, it certainly can be done. You have to provide a central reference clock source, and route that with matched trace length to each of your FPGA(s). If they are on the same board this is much easier to control than if they are on different boards, but it can be done. This reference clock should be lower in frequency (ie, probably in the 25 to 100MHz range) for ease of distribution.
On chip you can use the PLL capability of the FPGA and generate a higher frequency internal clock (eg, 200-400MHz) for use. Using the external reference you can phase lock the internal PLL generated clocks to the external reference clock at each FPGA, so you get internal clocks that are phase synchronous across devices.
At this point there will be an internal clock in each FPGA that is frequency matched across devices, and phase matched to some tolerance, that will depend on the external trace length matching tolerances, any external buffer delays, and the timing differences across different FPGA devices. What this will mean is that, within devices, you can determine that positive going clock edges will be coincident within some tolerance, like +/-NNNns.
It is doubtful you would be able to pass data synchronized to the clock between devices, given the skew tolerance buildup.
Personally I would not go this way as getting it to work reliably all the time is going to be a significant issue.
