Synchronous, asynchronous and synchronous asynchronous reset

[Altera_Forum]

Hello, 

 I guess this question was discussed quite often but I'm still a little bit lost here.  As far as I understood it Altera and also Xilinx are recommending synchronous asynchronous reset generation. This means the reset signal gets asserted asynchronously and deasserted synchronously.  My question is how should I implement the reset mechanism in my designs for the components which should be reset be the signal? I've created a component which triggers synchronously reset and a component which trigger asynchronously to the reset signal. Looking at the result in the Technology Map Viewer it looks like that an asynchronous reset logic is fitting better to the technology Altera uses.  Here is the example which Xilinx recommends for the reset logic (they have a document called libguide.pdf where one can look up the preferred coding style for logic elements):  process (clk)  begin  if clk’event and clk=’1’ then  if reset=’1’ then  data_out <= ’0’;  else  if force_high=’1’ then  data_out <= ’1’;  else  if enable=’1’ then  data_out <= a and b and c and d;  end if;  end if;  end if;  end if;  end process;   Does a similar document exist for Altera devices?   Best regards Martin

[Altera_Forum]

Registers in altera devices have async reset ports but no sync reset ports. You'll notice that async resets are generated as muxes on the d-input of a register. 

 But I would still recommend synchronous reset just as a good habit to have.

[Altera_Forum]

Tricky is right in that Altera register's have an asynchronous reset and if you don't use it, it's wasted. Making your reset synchronous will have that signal compete with other synchronous inputs, making the design a little larger and possibly slower. That being said, TimeQuest will analyze the signal feeding the asyncrhonous input of a register in a synchronous manner, which is called recovery and removal analysis. Look at Recovery and Removal on page 65 of the following guide: 

http://www.alterawiki.com/wiki/timequest_user_guide As explained, the recommendation is to build an asynchronous assert, synchronous de-assert circuit(it's only 2 registers). That gives you the benefits of an asynchronous reset but allows static timing analysis to look at the de-assertion and make sure everything in the system comes out of reset on the same clock. (I've found many companies, ASIC designers, etc. hav similar recommendations...)

[Altera_Forum]

Thanks a lot for your answers! I will stick to a synchronous asynchronous reset generation then and use asynchronous reset logic in my modules then for Altera devices.