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Altera_Forum
Honored Contributor I
1,622 Views

TCP Ethernet packet in FPGA?

Hi, 

 

I have a Cyclone IV GX transceiver kit. I want to observe TCP packets in signal tap in FPGA (and hopefully it'll be same as the one I observe in Wireshark) How do I do that? 

 

This is what I want to do: 

(1) step 1: Send a TCP packet to my own computer using a client program. 

(2) step 2: connect ethernet cable from my modem to the transceiver on my FPGA. 

(3) step 3 (greatest confusion here): get a clean packet (data, valid, start of packet, end of packet) into my FPGA. 

(4) step 4: observe packets in signal tap. Hopefully this will be the same I see in wire shark. 

 

How do I accomplish this? What IP's do I need to instantiate? Any help truly appreciated. I've never done anything like this before.... 

 

 

Thanks. 

giga
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10 Replies
Altera_Forum
Honored Contributor I
392 Views

If you are using the Altera Triple Speed Ethernet IP, the received packets come out in an Avalon Stream Source. You can include all the signals from this analog interface in the signaltap project, and use a conditional storage qualifier with both the ready and valid signals at 1. That way signaltap will only record the signals when there is an actual transfer taking place. Then add a trigger on the "start of packet" signal.

Altera_Forum
Honored Contributor I
392 Views

Daixiwen - thanks for the reply. The only thing I understood from your reply was the signal tap stuff. Can you please walk me (sorry :( ) through the IP's I should generating and instantiating? Right now I thought I could go through the Transceiver PHY IP Core User Guide. Is that a good place to start? I have this habit of reading irrelevant document and I usually go down the wrong path. Can you please walk me through it ? 

 

Really appreciate any help. I've also attached the IPs I see. I thought I could use 1G multi-rate Ethernet. But there are so many signals and I don't know where the inputs come from (analog interface). 

 

For now I'll google "Avalon Stream Source" and see how far I can get.
Altera_Forum
Honored Contributor I
392 Views

ghertz, 

 

What you are trying to do has a steep learning curve (but you have to start somewhere). I believe the kit you have comes with an example design in FLASH that they call "Board Update Portal". It should have the source code which is a good place to start.  

 

The board has a Marvell 88E1111 Ethernet Phy. The Phy is the interface between the physical cable and the digital parts of Ethernet (Layer 1 of OSI model). Inside the FPGA, you need to create an Ethernet MAC (Layer 2) that interfaces between the Phy and higher software layers. Altera provides the "Triple-Speed Ethernet" IP core for that purpose (ie TSE core). The first thing you have to do is create the TSE core with your desired options, instantiate it in your design. The signals in your EMAC that communicate with the Phy will be brought out to your top level design. Which ones depend on which Phy protocol you choose. There are many (MII, GMII ....). Like I said, there is a bit of a learning curve.  

 

You will then need code to initialize the EMAC and Phy. At that point, you can send packets from your PC and should see data come out in SignalTap. Normally, there would be software that interfaces to the EMAC (eg TCP/IP etc).  

 

It's almost impossible to do all this without and example, but the board comes with one.  

 

Normally, it is wise to read datasheets in detail, which you should do for the TSE. Unfortunately, Marvell makes it difficult to obtain their datasheets and you would be wise to find a board with a different Phy if possible.
Altera_Forum
Honored Contributor I
392 Views

corestat, 

 

Thank you so much. I just found opened the Board Update Protocol. This is exactly what I was looking for -- some sort of reference design. This is a good place to start. Let me see how far I can get. I'm curious. I'm not a TCP expert but I know TCP packets can arrive in any order. Who takes care of ordering them? Does it happen at the modem (coaxial cable in, and ethernet out) level. Basically I'll get ordered packets into FPGA correct? 

 

Thanks :)
Altera_Forum
Honored Contributor I
392 Views

Unfortunately I can't expand the board update protocol module and take a peak at the different instantiated modules. Now what do I do? :(

Altera_Forum
Honored Contributor I
392 Views

ghertz, 

 

TCP/IP is a very complex protocol and no, you will not get ordered packets into the FPGA. That is what the TCP/IP stack does. It also handles dropped and corrupt packets. The EMAC (TSE core for Altera) simply handles physically sending and receiving packets from the Phy which puts them on/off the cable. The TCP/IP stack is normally software in a processor that communicates via the EMAC. There is a company that makes a VHDL TCP/IP stack ( http://www.comblock.com COM-5402SOFT). I played with it and it worked pretty well.  

 

Just getting a TCP/IP packet to the FPGA takes some work. You will set a MAC and TCP/IP address for the Altera TSE EMAC. But when try and send a packet to the FPGA via a socket, the PC will first send out an ARP packet asking which device is at that TCP/IP. You will have to send an ARP response with your MAC address. When experimenting to just see a TCP/IP packet show up in the FPGA, I use a workaround of manually setting an ARP entry in the Windows ARP table. In a DOS command prompt, type "arp /?" and check out the -s option.  

 

Of course, if your FPGA is on a busy network, you will see a bunch of broadcast packets coming out of the EMAC without having to send anything to it. I normally take my PC and FPGA off our network when doing this sort of thing.  

 

I think it's great you're trying to learn this sort of thing. Dying breed.  

 

As you can see, it gets complicated pretty quickly. I learned TCP/IP many years ago via the classic set of books "TCP/IP Illustrated" by W Richard Stevens. There are others, and you can find online sources to get started. You will also need to understand the Ethernet Frame (see appendix in the TSE user guide). The Ethernet frame encapsulates the IP frame that encapsulates the TCP frame.
Altera_Forum
Honored Contributor I
392 Views

ghertz, 

 

I'm afraid I can't see the image you posted. It's too small. But it sounds like you need to become more familiar with the Quartus tools. The free Altera online training is very good: 

 

https://www.altera.com/support/training/catalog.html 

 

I'd select Course Type = Online, Language = English and Curriculum = "Fundamentals Part 1".  

 

I found "Become an FPGA Designer in 4 Hours" very helpful along with others.  

 

Although the Altera Quartus FPGA tools and training are great, their SoC tools and training are mind numbingly useless garbage designed by crazy people. If you want to use an FPGA SoC, which is probably smart if you need TCP/IP in a real application, you would be smart to switch to Xilinx. The Zedboard is an inexpensive way to get started and uses the free version of their tools. The Xilinx SoC FPGAs are, in my opinion, inferior to Altera, but their SoC tools make Altera look ridiculous. The Altera SoC tools are actually getting worse and I've been told they have no intention of fixing them. I was able to get a TCP/IP application up and running on a Zedboard in a few hours (follow Zynq Geeks tutorial). I've spent weeks on Altera tools and am still scratching my head.
Altera_Forum
Honored Contributor I
392 Views

Hmmmm how is the board protocol working then? Do they have TCP/IP stack implemented in there somewhere?  

 

Phew I am mentally exhausted just reading all this. So much to learn. I am not a complete newbie either. I have 5 years of industry experience. I still struggle with all this stuff. Not sure if that's normal. 

 

I started doing these things to once and for all get rid of "I don't know" how to do that feeling. I want to exercise all the components on the board. And just feel satisfied that I did something. Looks like TCP is a bad place to start. I know how to do these: 

 

a) program in verilog 

b) Access block rams inside FPGA fabric 

c) RTL/FSM design 

d) Meeting timing and some knowledge of timing closure. 

e) Generate IPs -- PLL, DCM, RAMs, etc.... 

 

All my insecurities/fears/whatever it is starts to crop up when I touch peripherals (i.e when I start to do something "real"). I guess I need to attack one component at a time.  

 

I'll set aside TCP for now. I thought I can should with something very simple. How do I get the SSRAM working? I looked at the Altera IP in Quartus I don't see anything called SSRAM controller. Any help truly appreciated. I think you are my Digital Design Teacher hahahaha. I'll do whatever you ask me to implement. I just want to feel secure in my skills :-|
Altera_Forum
Honored Contributor I
392 Views

The TCP protocop is typically handled by software. It's so complicated to do in hardware that you'd need a really good reason to do it in hardware. If you want to send or receive lots of data directly to a block of hardware and can live with packet loss or reordering UDP is a much simpler alternative. 

To answer your question, you must start by reading the datasheet of the component you need to connect to. You'll find information on how to use the control signals, and often some waveforms. From there you can write your module, a test bench that simulates the component, and test your code. Once it's working you can try and put it in the FPGA. 

 

I think you should see some tutorials about QSys and Avalon interfaces too. You'll learn how to add a processor to your system, connect different modules together and make your own modules. Depending on the SSRAM it may be just enough to add a "Generic Tri-State Controller" IP module to your system in QSys and connect the SSRAM directly to it.
Altera_Forum
Honored Contributor I
392 Views

ghertz,  

 

It's easy to get discouraged but at some point you'll hit the "oh, I get it" moment. I got the Xilinx RTOS + TCP/IP to work in a few hours but am still baffled by the Altera SoC tools after a week of head banging. So I can sympathize.  

 

However, it looks like the "Board Update Portal" example uses a NIOS II soft processor. The user guide does not say what operating system and TCP/IP stack is used, but I'd guess they are using niche stack TCP/IP stack and uCOS II.  

 

The NIOS II tools and training are actually pretty good. Not sure why Altera chose to have useless garbage tools for their latest and greatest SoC chips and great ones for a soft processor, but I don't run the world. In fact, as I remember, if you go through the NIOS II training, one of the examples is how to create a TCP/IP example.  

 

The user guide says the source code for the "Board Update Portal" example is in the: 

 

<install dir>\kits\cycloneIVGX_4cgx15_starter\examples 

 

directory. There will be two kinds of source code. The HDL code to create the hardware (including the NIOS II processor). But there should also be C source code showing how they run the web server. The TCP/IP stack is in C code running on the processor. It will make alot more sense if you work through the NIOS II online training.
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