New quartus prime user here.
Is it possible to use 625mhz clock input in max10 fpga?
Below is the screenshot of the compilation report where I'm getting warning under Timing analyzer.
Can anyone explain what the warning is and how to correct it.
Thanks for your inquiry. Referring to Table 27 in doc below
The max Fin supported is 472.5MHz, can you try if that resolve the issue? I am curious if you are using PLL?
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