Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
Announcements
FPGA community forums and blogs have moved to the Altera Community. Existing Intel Community members can sign in with their current credentials.
21618 Discussions

The issue of multiplier synthsis in Arria V

Altera_Forum
Honored Contributor II
‎02-03-2015 05:50 AM
1,038 Views

I get 20bit data from data bus and split it into two section, high 10bit and low 10bit. They are shifted left 6bit to form 16bit data respectively, I_16bit and Q_16bit. Then I_16bit is input into a multiplier with two input ports, and Q_16bit is input into another multiplier with input ports. Another input of these two multipliers is given a special data. The output of these two multipliers are added together to produce a result. But when carry out synthesis operation, these two multipliers are cancelled. Please give me a solution to avid this problem. Thanks a lot.

0 Kudos

Link Copied

0 Replies
Reply

Community support is provided Monday to Friday. Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.