The problem of Altera-SoCFPGA-HardwareLib-Unhosted-CV-GNU！

[Altera_Forum]

I want to debug Altera-SoCFPGA-HardwareLib-Unhosted-CV-GNU on terasic de1-soc and I don‘t know how to modify preloader to set up the UART appropriately(baud rate, parity, stop bits). 

Could someone help me?

[Altera_Forum]

You was choose correct direction ! 

And why at once modify and compile Preloader ? In .txt I see:   --- Quote Start ---  This Preloader was already compiled and it is provided with the project.  --- Quote End ---   Usually in Preloader HPS-UART is initialized with a necessary parameters and it's output is seen in UART console on host: U-Boot SPL 2013.01.01 (Jul 07 2014 - 11:47:21... However, the example is a little strange: I run program hello.axf as described in .txt (usual way) and stop in main(), step 2 lines, see output "Hello World!\n", then change PC in Registers window to 0x00100080 (entry point) in order to see in debugger all startup way, step a few times -- and program not run correctly ! I want certain of starting code avoids "SVC" commands. Then I add to Makefile a commands to generate .objdump: no "SVC" in disassemble. WHY ?!! :)  ...I try to boot from SD-card as described in .txt unsuccessful: using of  alt-boot-disk-util.exe -p preloader_scrubbing/preloader-mkpimage.bin -a write -d E return error "device open failed!".

[Altera_Forum]

Since my board is not Altera Cyclone V SoC Development Board rev D,I cannot use the precomplied preloader to debug this example. 

And I cannot find any information for how to modify the preloader to set up baud rate, parity, stop bits. Is there any altera documentation to explain how to use preloader to set up baud rate, parity, stop bits？

[Altera_Forum]

If Preloader starts, it at once outs to UART its messages. 

You see this through UART-USB cable ? At first out of Preloader, further -- Linux... Or in BootROM is initialising of UART on default values, or on start of Preloader... These settings is present in any Preloader or hard design ! Terasic give its sources of Preloader, not compatible with Altera-s ? In your HPS all devices is the same with Altera SoC, very strange is if HPS examples will not work everywhere.

[Altera_Forum]

The terasic only give the ghrd design based on de1-soc.But the Altera-SoCFPGA-HardwareLib-Unhosted-CV-GNU's preloader is different from ghrd design. 

The terasic's ghrd design can use for the Altera-SoCFPGA-HardwareLib-FPGA-CV-GNU example. So I think the Altera-SoCFPGA-HardwareLib-Unhosted-CV-GNU's preloader is modified. The Altera-SoCFPGA-HardwareLib-Unhosted-CV-GNU's u-boot-spl is 533K while the cv_soc_devkit_ghrd's u-boot-spl is 444K. So what‘s the different between them？

[Altera_Forum]

I think that will be need to probe Altera-s precompiled u-boot-spl in this or other examples projects :) Onchip HPS-UART may be initialized succsessful, SDRAM -- will be seen, all other isn't important. 

If not start all examples, run bsp-editor for your ghrd and make next changes:   --- Quote Start ---   - BOOT_FROM_SDMMC: checked  - FAT_SUPPORT: checked  - FAT_BOOT_PARTITION 1  - FAT_LOAD_PAYLOAD_NAME: hello-mkimage.bin  - WATCHDOG_ENABLE: unchecked  - SDRAM_SCRUBBING: checked  - SDRAM_SCRUB_REMAINING_REGION: checked  --- Quote End ---   UART parameters is ready by default ! You read section 3.7.3 of DE1-SoC_User_manual_0C0D.pdf about UART-USB onboard bridge ? The kit is connected to host PC with USB cable ? Drivers is installed for FT232R chip ? Putty or Hiperterminal is runned & displays spl-bsp output to UART on any example debug start ?..