The question about signal propagate in trace or cable

[Altera_Forum]

​There is a question about signal propagate in trace or cable which puzzle me for long time. I want discuss it here. 

  Assume two cases:   case 1: There are two chips connect with trace in the PCB. Chip A output siganls and the clock of signal to the Chip B (source sychrounous). The data and clock propagate in the trace. All the trace are length matched. But the length of all traces are long, which the time of signal propagate may cost 3 clock cycles.   case 2: There are two chips connected with cable. Chip A output serial signals to the Chip B using MGT. The cable is very very long like hundred metres. Therefore, signal propagte in the cable should take multple clock cycles based on serial data rate.   Now my question is: For case 1, will this cause timing issue? No matter yes or no, why? For case 2, I don't think it will cause problem. As I know we may use MGT to trasmitt signal between TX and RX which the distance between them may be hundred miles.    I think this question is more related to the physical question which is about the voltage distribution in the trace or cable. I hope I can make it clear here.   Thanks in advance.

[Altera_Forum]

My bigger concern here is signal integrity and managing that - I'll revisit this at the end. Ignoring that for now... 

 Case 1: This won't cause timing issues. If the propagation times for both clock and data are the same then there will be something there for you to use at the receiving end - even if the delay does amount to multiple clock cycles.  Case 2: Again, assuming no external timing influences then the receiving end of the MGT link can recover both clock and data successfully.  Back to signal integrity - you mention 'voltage distribution in the trace or cable'. You also mention 'hundred metres' & 'hundred miles' - both pretty tough challenges. If these distances are to be covered for either case 1 or 2 you are going to need additional buffering/boost circuitry. I would immediately be looking for an off the shelf solution (like a Gb Ethernet Phy) to do all the hard bit for me.  This option aside; whatever external circuitry you add is going to introduce jitter, which will reduce you're ability to recover the data at the receiver. In the case of data & clock you will also end up with a skew between them, which will likely be different board to board - i.e. non-characterisable, therefore not a workable as a solution. The compromise will be a trade off between data rate and distance.  Cheers, Alex

[Altera_Forum]

Thanks, Alex. 

 Yes, I just take the " hundred metres" as an example, I know we need a lot of other things if we really need trasmitt signals in that long distance. I think nobody will transmit parallel data in that long distance.  For case 1, your answer is This won't cause timing issues. Then I think there is an interesting case inside FPGA.  Assume If I have a very long path inside the FPGA, that the signal propagating that path needs more than one clock cycle (assume it arrives the destination FF before 2nd flip-flop). But this is just initial delay, the later data still arrives destination FF cycle by cycle. If I made my design in the destination FF to work as this delay, then my design should work, there should be no timing issue in my design, right?  Definitely, I need proper timing constrain in sdc file to make Quratus II STA to understand my timing to avoid timing failure problem.  Thanks.