Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
Announcements
Need Forum Guidance? Click here

Search our FPGA Knowledge Articles here.
18950 Discussions

The speed of the M9K and Embedded multiplier in Cyclone 3?

Altera_Forum
Honored Contributor I
1,687 Views

Hello, would you please point me to this information. From long time ago I recall that M9K is 5 ns r/w cycle, but can not find reference any more. The question rose because I use 112.5 MHz clock to operate M9K block and 8*8 signed embedded multiplier, and need to know if there could be any problem at this speed. Thank you.

0 Kudos
5 Replies
Altera_Forum
Honored Contributor I
310 Views

Look at the cyclone iii device datasheet (https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/hb/cyc3/cyc3_ciii52001.pd...), see the 'embedded multiplier specifications' & 'memory block specifications' on page 1-16. I hope that tells you what you need to know. 

 

Cheers, 

Alex
Altera_Forum
Honored Contributor I
310 Views

Thank you! Altera has a lot of documents on the same chip, and information is fragmented... I was looking into the handbook, this info is missing there. 

So I am safe at 112.5 :)
Altera_Forum
Honored Contributor I
310 Views

Hi Eugeny: 

 

I would still take the specifications given in the datasheet with a grain of salt. That's the maximum speed of the Memory block/Multipliers themselves. But routing and other logic pipelining usually is the limiting factor. 

 

At 112.5 MHz you shouldn't have any issues. I have an FFT block with 18x18 multipliers running at 160 MHz in a Cyclone III design. 

 

Pete
Altera_Forum
Honored Contributor I
310 Views

The information in the datasheet is the best case max speed - with no routing in or out of the parts. The FMax your design can acheive is dependent on your code.

EugenyB
New Contributor I
285 Views

6 years later I have similar question. I need multiplier for 24*32 bits, a huge one, and Quartus says it needs eight 9x9 multipliers and 84 LUTs.

But the subject of cascaded multiplier is not covered anywhere in detail. From marketing perspective discussed here things are perfect, but it is not clear how well cascaded multipliers perform (as I guess decent DSP will need bigger multipliers than 18x18 and this MUST be covered somehow), and connection circuit is also not clear.

By the way, this material says:

>The embedded multipliers are also seamlessly integrated with the embedded memory blocks in Cyclone III FPGAs. This provides an efficient implementation of DSP algorithms that uses both multiplication and memory operations, such as FIR filters and video processing.

I am doing exactly this - FIR design, and want to know how cool Cyclone architecture helps me in doing it best way. Does it assume using FIR IP core? I see its interface is serial, and timing is not clear (at least learning how it works will be more effort and time than designing own), so I would better design my own.

Reply