I'm trying to interface a cyclone II device to an (asynchronous) SRAM (DE2 board). I have a written memory controller, and for a read operation I wait for several clock cycles (25Mhz) with the address registered and ce/we/oe with the proper values - and after a fixed period of time has passed - I sample the SRAM output data inside the FPGA. a second feature I have is registering the address and at next clock edge - registering the SRAM data outputs (asynchronous path: FPGA address reg --> SRAM address inputs --> SRAM data outputs --> FPGA data inputs). I would like to constrain the path with the TimeQuest by setting the input / output delay. what I had in mind is setting the output delay to: outputdelay_max=board_delay+SRAM_read_delay+Tsu (FPGA clock setup, since the sampling clock is the FPGA's clock itself). am I wrong? should I try a different approach? and can I use the latter and not introduce an input delay? Thanks in advance, Eyal.