Timing Problems in ALTLVDS_RX (Cyclone 3 and 5)

[Altera_Forum]

Hi, 

I am planning to use Cyclone3 FPGA in my new design. I am evaluating the idea on Cyclone 5 FPGA at present. My design involves capturing an ADC's digital output (rate=876Mbps) at ADC's output clock (frequency=438MHz). The ADC's digital output is 'serial data' ie a serial stream of 7bits on same wire. So, I am using FPGA's ALTLVDS_RX block to latch and deserialize the data stream. The serial data is available on both edges of latching clock. Now, for a stable deserialization, I must specify the setup and hold time of serial data (which is input to the FPGA) with respect to ADC's clock (which is latching clock of the deserializer block ALTLVDS_RX). Available data setup time for data is 400ps and hold time is also 400ps (at serial data rate of 876Mbps). See the attached picture for more details. I am trying to use time quest timing analyzer to generate sdc file from setup and hold time constraints. The analyzer generates the sdc file (it generates max and min delay basically from setup/hold constraints I pass to it) and compilation successfully completes. But the deserialized data is neither reliable nor per expectation and suggests timing problems in latching ADC data. Sometimes it works at serial data rate of 876Mbps but fails at 870Mbps though setup/hold timings wouldn't have changed much by small changes in serial data rate. Now, if I set "what is the phase alignment of 'rx_in' with respect to 'rx_inclock' parameter" to 90 degree (from default settings of 0 degree), the serial data is latched properly by ALTLVDS_RX over a range of data rates (from 876Mbps to 700Mbps). This makes me wonder if specifying setup and hold time in sdc file has any role to play in latching serial data by ALTLVDS_RX. Even if I provide an arbitrary setup/hold time in SDC file, should the ALTLVDS_RX keep deserializing properly? How do I ensure the ALTLVDS_RX latches the serial data based on timing constraints I provide in SDC file? Regards, Sourabh

[Altera_Forum]

Hi, 

Can someone please help on this? Regards, Sourabh