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Timing closure of DDR3 Soft Memory Controller @533MHz
I am trying that DDR3-SDRAM controller works @533MHz with Arria V (speed grade 4). But timing failures have happened, I can't solve still now. I want to use a Soft Memory Controller than Hard, because burst length can be set above 128 words. So I use half-rate clock as Avalon-MM interface, but about minus 2ns slacks to 3.75ns(266MHz) exist inside qsys_mm_interconnect module. Actually f-max of half-rate clock is about 150-200MHz in my design. I heard that the max speed is 667MHz when using Soft IP, so that it should work @333MHz with half-rate clock. Possibly I guess the quarter-rate clock should be used if it works @667MHz, is it only method ? Do anyone know a case that work above @533MHz with half-rate clock ? I would like to avoid that Avalon-MM bus width will be twice..(but I will choose quarter-rate clock if it's only way.) Infromation: The version of Quartus II is 15.0.0 . The device we choose is 5AGXFB3H4F35C4 DDR3 data width is 32bit. (FPGA Internally, 64bit @533MHz, 128bit @266MHz) # After I editted my thread yesterday, my thread body has been seen any more.# So I re-post this.Link Copied
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I heard from a foreign Altera agent that DDR3 half rate soft controller in Arria V can't support 5333MHz, maximum frequency is 400MHz.
So I need to use quarter rate. This thread is now closed.
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