Programmable Devices

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Programmable Devices

Discussions

Lead free vs. leaded packages

LVDS in Stratix II / Cyclone II – Do I have to use 2.5V?

IBIS & modelling Hi-Z

adding jam file to Quartus

Calculating jitter

VCCA power for PLLs

Cyclone I/O leakage current

Frequency of the internal oscillators during initialization?

"Power Pair" in Cyclone II

Wide MACCs in Stratix III

does LVDS input clock have internal bias?

changing PLL parameters to get desired PLL Implementation

Simulation of PLL lock time

how to connect unused reserved pins on the board

DCLK frequencies are supported by EPCS?

Featured Content

FPGA passive serial configuration -- detect as PCIe device in Linux after configuration

Converting Oscillator HCSL Output to SSTL_18

simulation for the HBM2E Interface FPGA IP

Re: The rx_is_lockedtoref in Native PHY cannot be stabilized at 1

Re: Enable on-chip termination for Differential Transceiver clocks

Re: Quartus 18.1 & DE2-115

Re: Quartus programmer start failed

FPGA passive serial configuration -- detect as PCIe device in Linux after configuration