Timing constrain setting for uart

[lipingx]

I am thinking about how to set timing constrain for uart. It's actually sampled by FPGA internnal system clock. For example, if uart baudrate is set 115200 bps, I use FPGA pll clock = 50MHz is quite enough to sample each bit. But there is no external clock input for uart rxd or txd. So I think we don't need to do any set_input_delay or set_output_delay for rxd or txd. It doesn't matter how long it delays externally. There is no impact of FPGA to detect uart data. I need to set_false_path to and from for rxd and txd. Please let me know if my understanding is right and what's your common practice to handle uart rxd and txd pin for timing constraint setting.

[ak6dn · Accepted solution]

Your observations are correct. You are sampling an asynchronous signal using (I expect) a dual rank clocked synchronizer approach. So there is no timing constraint (setup/hold) applicable on the data input to that input register. It is totally asynchronous.

I have a very similar UART module in a design I have that samples the RX input at 50MHz. In the .sdc file I have:

   set_false_path -to [get_ports {UART_*}]

and no other timing constraints on the UART_* inputs.

[Nurina]

Hello,

Does above comment help?

Regards,

Nurina

[lipingx]

Yes, thanks!

[Nurina]

Hi,

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