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Timing constraint for clock divided by timer

XShen1
Novice
203 Views

Hello,

I am doing timing constraint for serial adc ic as below verilog code.
clk below comes from system clock from a pll, and divide clock by 250 through timer.

Question 1) :so I define adc_sclk as below, is it right?
create_generated_clock -name adc_sclk -source [get_pins {clock_pll_0|altpll_component|auto_generated|pll1|clk[0]}] -divide_by 10 [get_pins {adc_driver_3|timer[0]|q}]

Question 2): for timing constraint for adc_cs, should I define multicycle path as below or just set max delay or set false path?
set_multicycle_path -from [get_clocks {clk}] -to [get_clocks {adc_sclk}] -setup -end 250


module iadc_driver(
clk, //50MHz
reset_n,

adc_cs,
adc_data,
adc_sclk
);


always @(posedge clk or negedge reset_n) begin
if(reset_n == 1'b0)
timer <= 16'd0;
else if(enable == 1'b0)
timer <= 16'd0;
else if(timer == 16'd249)
timer <= 16'd0;
else
timer <= timer + 16'd1;
end


assign adc_cs = (timer <= 16'd5 || timer > 16'd200);

assign adc_sclk = ( timer < 16'd10 ) ||
(timer >= 16'd15 && timer < 16'd20 ) ||
(timer >= 16'd25 && timer < 16'd30 ) ||
(timer >= 16'd35 && timer < 16'd40 ) ||
(timer >= 16'd45 && timer < 16'd50 ) ||
(timer >= 16'd55 && timer < 16'd60 ) ||
(timer >= 16'd65 && timer < 16'd70 ) ||
(timer >= 16'd75 && timer < 16'd80 ) ||
(timer >= 16'd85 && timer < 16'd90 ) ||
(timer >= 16'd95 && timer < 16'd100) ||
(timer >= 16'd105 && timer < 16'd110) ||
(timer >= 16'd115 && timer < 16'd120) ||
(timer >= 16'd125 && timer < 16'd130) ||
(timer >= 16'd135 && timer < 16'd140) ||
(timer >= 16'd145 && timer < 16'd150) ||
(timer >= 16'd155 && timer < 16'd160) ||
(timer >= 16'd165 );


always @(posedge adc_sclk or negedge reset_n) begin
if(reset_n == 1'b0)
adc_data_shift <= 16'd0;
else if(timer < 16'd150)
adc_data_shift <= {4'd0, adc_data_shift[10:0], adc_data};
end

 

 

0 Kudos
2 Replies
KhaiChein_Y_Intel
182 Views

Hi,


You have to constrain the signals:

Clock - create_clock

PLL - create_generated_clock or derive_pll_clock

adc_sclk - create_generated_clock

adc_data - set_input_delay

adc_sc - set_output_delay, false path and multicycle constraints depending on your design. You may refer to this document https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/an/an433.pdf


Thanks

Best regards,

KhaiY


KhaiChein_Y_Intel
167 Views

Hi,

We do not receive any response from you to the previous question/reply/answer that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you


Best regards,

KhaiY


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