Hi,
The maximum delay is similar to changing the setup relationship (latching clock edge - launching clock edge). Maximum delays are always relative to any clock network delays (if the source or destination is a register) or any input or output delays (if the source or destination is a port). Therefore, input delays and clock latencies are added to the data arrival times. Clock latencies also added to data required times and output delays are subtracted from data required times.
You can also use the set_net_delay command to specify the minimum delay, maximum delay, or skew for any edge in your design when no clock relationships are defined or required.
According to Timing Analyzer UG (Chapter 2.2.8.1 https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/archives/ug-qpp-timing-analyzer-19-1.pdf), set_false_path has higher timing precedence than set_max_delay. If the same clock or node names occur in multiple timing exceptions, the first one will take place. set_net_delay exceptions analyze independently of minimum or maximum delays, or multicycle path constraints. The set_net_delay exception applies regardless the existence of a set_false_path exception, or set_clock_groups exception, on the same nodes.
Thanks
Best regards,
KhaiY
