Total execution time and propagation delay

[Altera_Forum]

hi, 

How to calculate total execution time and propagation delay for VHDL files under Quartus II? Thank you

[Altera_Forum]

If you aren't familiar with the tools or the code you're dealing with, probably the easiest and simplest way is to run a ModelSim simulation and treat it like a black box: apply known inputs and wait for known outputs to show up.

[Altera_Forum]

Thank you, for your reply. 

Kindly note that, I have 3 inputs 256 bit each which takes a long time under modelsim to simulate it.  I am looking for a short way to calculate execution time and propagation delay. I got the Fmax, but what are the equations that I should apply in order to get execution time and propagation.

[Altera_Forum]

--- Quote Start ---  Hello aaabbb, I have same problem, have you any ideas how to calculate the total time and propagation delay on Quartus II? Thank you  --- Quote End ---    The timing analyser will ensure that your design meets the timing specifications that you give it. Assuming you mean latency when you refer to "execution time", then you can easily work this out from the number of registers in the pipeline.

[Altera_Forum]

--- Quote Start ---  The timing analyser will ensure that your design meets the timing specifications that you give it. Assuming you mean latency when you refer to "execution time", then you can easily work this out from the number of registers in the pipeline.  --- Quote End ---    Hi Tricky,  Thank you for your answer. I have, for example, an adder 4 bits and i want to calculate the "hardware execution time" for this adder. After compiling the code, and by using "TimeQuest Timing Analyser", i got the attached "Propagation Delay". Knowing that the total "propagation delay" is taken as the "hardware execution time", how to calculate the total "propagation delay"? In the attached file, i have RR=RF=FF=FR, is it normal??  Best Regards,

[Altera_Forum]

This is not a execution time, this is the propogation delay through this circuit for this compilation in the worst case scenario. Next time you compile the code, this will change. Timequest is only meant to tell you if your design met the timing specs that you specified or if it missed. It is meant for synchronous designs only. Relying on propagation delays through the device is NOT reliable, as they will be affected by PVT (process voltage and temperature) ie. as the temperature changes, so will the propogation delay. To mitigate this you use a synchronous circuit, then you know what the register-register timing is, and timequest can tell you if your design can meet it.

[Altera_Forum]

--- Quote Start ---  This is not a execution time, this is the propogation delay through this circuit for this compilation in the worst case scenario. Next time you compile the code, this will change. Timequest is only meant to tell you if your design met the timing specs that you specified or if it missed. It is meant for synchronous designs only. Relying on propagation delays through the device is NOT reliable, as they will be affected by PVT (process voltage and temperature) ie. as the temperature changes, so will the propogation delay. To mitigate this you use a synchronous circuit, then you know what the register-register timing is, and timequest can tell you if your design can meet it.  --- Quote End ---    Thank you Tricky, you are right. If the "Total Propagation Delay" is not a "Hardware Execution Time", so how to calculate the "Hardware Execution Time" of my adder 4-bits. The code of an adder 4-bits is attached.   Best Regards,

[Altera_Forum]

There is no such thing as "hardware execution time". 

You have no clock in your design, so the circuit will have a propogation delay as I described previously.  if you had a clock in the design, then you could calculate the latency.

[Altera_Forum]

--- Quote Start ---  There is no such thing as "hardware execution time". You have no clock in your design, so the circuit will have a propogation delay as I described previously.  if you had a clock in the design, then you could calculate the latency.  --- Quote End ---    I would like to calculate the time required to execute this adder in hardware(FPGA) and in Nios ii. have you any proposition to do this??

[Altera_Forum]

--- Quote Start ---  I would like to calculate the time required to execute this adder in hardware(FPGA) and in Nios ii. have you any proposition to do this??  --- Quote End ---    With the current code, that is impossible as it is an asynchronous (no clock) process Make it synchronous, and then you will know the latency ie. how many clocks are required to complete the operation.

[Altera_Forum]

--- Quote Start ---  With the current code, that is impossible as it is an asynchronous (no clock) process Make it synchronous, and then you will know the latency ie. how many clocks are required to complete the operation.  --- Quote End ---    When i add a clock in my code i get a negative slack. I searched how to avoid this problem but i haven't found.

[Altera_Forum]

What clock speed have you specified in your SDC file? without one, Timequest will check the timing at 1000Mhz (which is much faster than is realistically acheiveable). But it will report the fmax for the circuit (which is the fastest clock speed you could run the design at).

[Altera_Forum]

--- Quote Start ---  What clock speed have you specified in your SDC file? without one, Timequest will check the timing at 1000Mhz (which is much faster than is realistically acheiveable). But it will report the fmax for the circuit (which is the fastest clock speed you could run the design at).  --- Quote End ---    Thank you Trichky,         Using your informations i was able solve problems. Now i have a synchronous adder without errors. So, how to calculate the total execution time of this adder by using "TimeQuest Timing Analyser" ?      Best Regards,

[Altera_Forum]

You dont. 

You count the number of registers in the pipeline and that is your latency (probably what you mean by ttotal execution time).

[Altera_Forum]

--- Quote Start ---  You dont. You count the number of registers in the pipeline and that is your latency (probably what you mean by ttotal execution time).  --- Quote End ---    I mean by "total execution time", the time required to execute the circuit(Addr) in the fpga.

[Altera_Forum]

A circuit does not "exectue" inside an FPGA - it always exists, and is always running. It is a circuit, not a piece of software.

[Altera_Forum]

--- Quote Start ---  A circuit does not "exectue" inside an FPGA - it always exists, and is always running. It is a circuit, not a piece of software.  --- Quote End ---    If a circuit does not "exectue" inside an FPGA, why it has a Fmax? Can we not consider T=1/Fmax a minimum execution time of a circuit?

[Altera_Forum]

The Fmax is the maximum frequency you can run the clock at. The circuit may have a latency of 10 clocks, meaning it takes 10 clock cycles to get a value from the input and calculate a result, but you are able to input 1 new data value on every clock cycle because all you are doing is feeding data into a pipeline.  

 FPGAs contain circuits, not programs.

[Altera_Forum]

--- Quote Start ---  The Fmax is the maximum frequency you can run the clock at. The circuit may have a latency of 10 clocks, meaning it takes 10 clock cycles to get a value from the input and calculate a result, but you are able to input 1 new data value on every clock cycle because all you are doing is feeding data into a pipeline.   FPGAs contain circuits, not programs.  --- Quote End ---    Forme, the time required to calculate the result using inputs values is "the total execution time", and i want calculate it. If the latency is the same as the "total execution time", how can we calculate it?

[Altera_Forum]

You just work out how many registers are in the pipeline. You can easily do that from the code/simualtion.

[Altera_Forum]

--- Quote Start ---  You just work out how many registers are in the pipeline. You can easily do that from the code/simualtion.  --- Quote End ---    I am not accustomed to do that(I am a beginner). Have you a tutorials that deal this topic?