Transceiver placement issue

[Altera_Forum]

Hi, 

In my current design using a Cyclone IVGX, EP4CGX50DF27C6 chip, there is a 4 lane PCIe interface. It works well. Now i need to add another transceiver to connect to a 10Gbps interface which is a 4 lane basic serdes structure. It should be OK for those total 8 channel application, 4 channels for PCIe and another 4 channels for a transceiver. When i add the new transceiver (ALTGX) to my current design, Quartus fails in placement stage, and shows me the following error message,  //--------------------------------------------------------------------------------------------------------------------------------------------------------------------- Error (167005): Can't assign I/O Input Buffer "mux_rx_in0~input" to PIN_N2 because this causes failure in the placement of the other atoms in its associated channel  Error (167009): Quartus II software cannot combine the following Calibration block(s) due to inconsistent parameters and/or input connections  Error (21087): Input port "CLK" must be driven by the same source  Info (21090): Atom "ahip4_top_gen1_c4gx:top|ref_design_epcore_4x125_gen1_c4gx:ahip|ref_design_epcore_4x125_gen1_c4gx_serdes:serdes|ref_design_epcore_4x125_gen1_c4gx_serdes_alt_c3gxb_n3h8:ref_design_epcore_4x125_gen1_c4gx_serdes_alt_c3gxb_n3h8_component|cal_blk0" is driven by source "ahip4_top_gen1_c4gx:top|pll_25_config:pllreconfig|altpll:altpll_component|pll_25_config_altpll:auto_generated|wire_pll1_clk[1]"  Info (21090): Atom "ti_lane_alignment:access_controller|mux_xcvr_4lane:la_serdes|mux_xcvr:mux_xcvr_inst|mux_xcvr_alt_c3gxb:mux_xcvr_alt_c3gxb_component|cal_blk0" is driven by source "pll25_reconfig_mux:pll25_reconfig_mux_inst|altpll:altpll_component|pll25_reconfig_mux_altpll:auto_generated|wire_pll1_clk[0]" //----------------------------------------------------------------------------------------------------------------------------------------------------------------------  Quartus refuses to implement the new transceiver at other 4 channel locations. I guess Quartus consider the all eight channels as one transceiver. I don't know why. Is there any guru can give me some hints?   Very appreciated!