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Hi All,
I don't undestand in FLEX 10KA. How does "Individual tri-state output enable control for each pin" work. How I can select between Tri-state output and OpenDrain output with IDE MAX+plus II. Where I can read about this? Thanks.Link Copied
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You implement an opendrain ouput by using a Tristate output.:
Pin = tri.out; tri.in = gnd; tri.ena = data; You can find the tri primitive ( AHDL ) in maxplus II at: help->primitives succes, Andries- Mark as New
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Hi, Andries! Thanks for answer.
I am reprogramming now the old project on the chip FLEX 10K30A and wont to use Verilog HDL. The FPGA connects to RAM with the tri-state buses in 32-bits. When I implement the primitive TRI(in, oe, out), FPGA forms only 0,z states (It was open drain, I think). And all was OK with 0,1,z states when I implemented graphic primitive TRI from library c:\maxplus2\max2lib\prim in the graphic’s mode (It was full tri-states output, I think). In both cases I used TRI primitive. Why does it occur? Why I can’t work with tri-state buses in Verilog HDL and can only in *.gdf? What is wrong? Best regards, Serhiy.
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