Triple-Speed Ethernet - Verilog TX/RX example

[vmetodiev]

Dear Community,

Recently I have been struggling  to find a real-world Verilog example for (single) frame Ethernet TX/RX. I have successfully imported and synthesized the Triple-Speed Ethernet IP core on the Cyclone 10 LP kit. However, this where I got stuck. The IP core documentation confuses me, since it suggests using several TCL scripts that I am trying to avoid - it is not clear to me how they utilise the generated Top.v module at all.

May anyone help me with a simple example to transmit/receive a single Ethernet frame via Verilog code with the generated IP core? I need a completely bare-metal, processor-less and Avalon-less functionality. Just a simple "transceiver", maybe with a minimalistic FSM only.

Thank you in advance!

[Paveetirra_Srie]

Hi Varban,

There are few simple option available in Intel website for Verilog Design Example. You may refer to it.

Kindly do let me know if you needed further support.

https://www.intel.com/content/www/us/en/support/programmable/support-resources/design-examples/horizontal/verilog.html

Regards,

Pavee

[vmetodiev]

Hi @Paveetirra_Srie ,

Thank you for your response, but the provided examples will be not sufficient in the context of an Ethernet transaction with the Triple-Speed IP Core. 

Kindly do let me know if you needed further support.

--> So... my answer is: yes, I will need further support, if possible!

[Paveetirra_Srie]

Hi,

Good day to you.

I believe you're working with Cyclone 10 devkit with TSE IP. We do have a reference design for TSE IP. Link provided below.

Kindly do let me know if you've tried this.

https://www.intel.com/content/www/us/en/design-example/714768/cyclone-10-lp-intel-fpga-triple-speed-ethernet-and-intel-on-board-phy-chip-reference-design.html

Regards,

Pavee

[vmetodiev]

Hi Pavee,

Yes, exactly, my question is based on the TSE IP and the official example for the Cyclone 10 LP that you have mentioned.

I am able to compile the IP, flash the FPGA over the USB-to-JTAG and run all of the TCL tests from the System Console.

However, I do not want TCL and Avalon-ST. 

I need simple Verilog examples on top of the TSE IP, with send/receive FSM funcionality. 

[Paveetirra_Srie]

Hi Varban,

Thanks for confirming. Unfortunately, we don't have example design based on your requirement.

I believe you can refer to UG below. It has prompt explanation on State machine Verilog.

https://www.intel.com/content/www/us/en/docs/programmable/683082/22-3/verilog-hdl-state-machines.html

[Paveetirra_Srie]

We do not receive any response from you to the previous answer that I have provided. This thread will be transitioned to community support. 

If you have a new question, feel free to open a new thread to get the support from Intel experts. 

Otherwise, the community users will continue to help you on this thread. 

Thank you.