Trying to make ALTPLL block working for me.

[Altera_Forum]

Hello, 

 The question relates with using the ALTPLL core and Quartus II  I have inherited a Verilog design. In this design I see they have used altpll core.  The input clock of the altpll is 72MHz coming from an external oscillator true a pin of the FPGA Based on this clock the PLL is deriving 72MHz, 144MHz and 576MHz. I have put the available 144MHz clock on external pin and confirmed with oscilloscope that it is indeed stable 144MHz.  This PLL has some unused output channels so I decided to use it for 288MHz I need in my design. I have enabled the c1 channel and set the parameters (please see the picture).  I have routed out this new clock to the output pin but I don't get 288MHz. What I get is some osculations on this pin just after reset with variable frequency and after 1 seconds they stop. Initially I have thought that 288Mhz is too high so I made it 144MHz. (same as I already have on c2)  So I copied same output clock parameters as c2 into c1 but to my surprise I still don't get stable clock on c1. Whatever frequency settings i tested I can not get stable oscillations on c1   I am about to put another separate altpll instance in order to double from 144 MHz to 288Mhz and test,  but obviously it will be stupid solution (assuming it works.)  Anyone having an idea what could be wrong ?  Thank you Dimitar

[Altera_Forum]

Two days already not much progress. 

I got some observations however:  1. At the end I found out that changes in the MegaWizard for the ALTPLL core doesn't change the behavior at all.  This design is pretty old and originally is done with Quartus II 11.0. Now I am using Quartus II 14.0.   Do you think this may be the problem?  2. In this design two ALTPLL cores are instantiated.   In the Hierarchy view I see those as two separate "magic stick" items but if I double click I get same parameters for both items.   (Adjusting the parameters for the first instance goes to the second automatically )  For the test I have disabled the second ALTPLL instance and i I saw the PLL count in the final compilation report decreasing with one,  so definitely those two instances represents two independent hardware blocks.  Why Megawizard looks at them as a single hardware block?     I am getting very confused

[Altera_Forum]

Problem solved.  

The PLL in this design was reconfigured on the fly and this was something I was missing.