When I use RapidIO in Arria 10 to communicate with DSP , I find port_initialized of IP core is high , but the port_ok of the port 0 error and status CSR-offset:0x158 is low. According to RapidIO Gen1 Debug Checklist of INTEL FPGA WiKi , I check the steps of Unable to establish a link , but the issue still exist.
When DSP complete the initialization, the port_initialized of FPGA IP core is high, but CSR 0x158 = 1 ,
the PORT_UNINIT of this register is 1, the PORT_OK of this register is 0 . Besides I find the
no_sync_indicator is 1. What maybe bring on unable to establish a link.