Use DIMM with two DQS pairs swapped?

[Altera_Forum]

I have a prototype board that uses a DDR2 SO-DIMM. Due to a design error, the DQS6 and DQS7 pairs are swapped. Would the design still work?  

 The DDR interface is very slow on this board and all 64 bits are written and read at the same time by my custom logic. This should have the effect that all DQS pairs should be driven at the same time such that having two of the pairs swapped should not matter (except for a slight timing difference).  The question is: Is the HPCII DDR2 controller using the DQS strobes individually during initialization? If so, then the swapped pairs may cause things to break.  It may be possible to rework this board but if it works anyways, I may not need to (very hard to fix up traces around the SO-DIMM socket).  The device is an Arria II GX.  Thanks!

[Altera_Forum]

By design do you mean on the PCB? just swap the entire DQ group pinouts in the FPGA design.

[Altera_Forum]

--- Quote Start ---  By design do you mean on the PCB? just swap the entire DQ group pinouts in the FPGA design.  --- Quote End ---    IMO that won't work. The HPCII PHY makes use of the DLsL to phase-shift the incoming DQS signals on read. So the ALTMEM_PHY may get confused on initialisation.  The best option to salvage the board is to write your own custom PHY using a PLL- generated phase to clock in the read data. At low frequencies this should be feasible, even easy at 125 MHz. If you feed the clock out on a free DPClk pin and route it back in (by forcing this in the Assignment Editor) the 'read clock' will track the silicon variation due to temperature and process quite close. But you may best first try the HPCII as is - using the heat gun to see if it holds.

[Altera_Forum]

You can switch around any DQ groups. The PHY doesnt care and the user is invisible to it as the mix up on the way to the memory gets corrected on the way back.

[Altera_Forum]

--- Quote Start ---  You can switch around any DQ groups. The PHY doesnt care and the user is invisible to it as the mix up on the way to the memory gets corrected on the way back.  --- Quote End ---    It would have made me think a bit harder if you had added that to your previous post. I still think that swapping the DQs is not correct, because physically the received DQS doesn't match the sent DQx as both sets will be from different DDR2 chips whereof one may be 'slow' and the other 'fast' silicon. Writing will work fine as the timing depends on the FPGA only.  I'd rather suggest to try if e.g. John has connected say FPGA-DQS0 to SoDIMM-DQS1 (and FPGA-DQS1 to SoDIMM-DQS0) to swap The DQS pins on the FPGA side and rely on the fitter to route everything. So the DQS0 pin would end up in the DQ8..15 IO bank and DQS1 in the DQ0..7 IO bank.

[Altera_Forum]

Thanks for all your suggestions. I'll get the board back from assembly next week. If it doesn't work as-is then I'll try swapping the DQ-groups. If that doesn't work then I'll patch the board.

[Altera_Forum]

I misread the original issue. If just the DQS pins are swapped then you need to rework the board. The DQS pins must be matched the to DQ group on the FPGA.