Use FPGA to reclock audio I2S/ADAT/SPDIF signals

[lelsteph]

Hello,

I am completely new to FPGA / CPLD Any help or guidance will be really appreciate!

I am looking for a way to reclock audio spdif/adat/i2s signal to remove jitter. It seems I can use some Altera FPGA.

I do not want to re-invent the wheel.

Do you know if some application examples, application notes etc... are available?

Thank you very much!

Stephane.

[Ash_R_Intel]

Hi,

Can you be more specific in the requirement here? Are you looking for a PLL reference design or any specific protocol?

Regards

[Ash_R_Intel]

There are several reference designs available for reference. Please check below links:

FPGA Wiki - Intel Communities

Intel® FPGA SDK for OpenCL Design Examples | Intel

Regards

[lelsteph]

Hello

I am looking for a solution to reclock:

- COAX SPDIF

- OPT SPDIF

- I2S (2 channels)

with extremely low jitter < 100-200fs.

An XMOS is generating above streams.

Plan is to use extremely precise clocks like Crystek or Accusilion 45.1584MHz & 49.152MHz (or multiple).

The "re-clocker" would take the COAX SPDIF and the OPT SPDIF and from above clock will reclock the signals by sending the clock back to the XMOS to get the data bits.

The "reclock" would take the I2S signals: CLK, LRCLK, DATA and reclock using above clocks.

There are tons of such boards on the market using Intel FPGA so I am quite sure this was already implemented. I do not want to re-invent the wheel

Thank you for any help!

Stephane.