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Using Cypress FX3 as device for Passive Serial

Altera_Forum
Honored Contributor II
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Hey, 

 

So I'm working on a setup with the Cyclone 3 (specifically EP3C5E144C8N), which uses a Cypress FX3 board as the passive serial initialisation device. Unfortunately I cant seem to get the device to successfully complete initialisation. So Far I have made sure the following things are in working order. 

 

- Bytes are shifted out LSB first from the FX3 

- The .rbf file that I export from quatrus is for the correct device and passive serial configuration 

- The nConfig and nStatus timings are correct 

- The clock for the data stream is 25MHz (less than the 100MHz max) 

- The MSEL pins are the necessary configuration (000) 

 

The only thing I can find that is going wrong is that nStatus occasionally drops low during the configuration process. 

 

I have it connected to and oscilloscope so I can upload waveforms and circuit diagrams if necessary. 

 

Kind Regards
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Altera_Forum
Honored Contributor II
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How are you connecting the FX3 board to the FPGA ? Are you using the provided HSMC connector and interfacing the FX3 board with the FPGA board? Is this your FX3 kit? 

 

http://www.cypress.com/documentation/development-kitsboards/cyusb3kit-003-ez-usb-fx3-superspeed-explorer-kit
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Altera_Forum
Honored Contributor II
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nSTATUS going low before configuration completes indicates the FPGA has detected an error. 

 

I'm concerned about the relative timing between the clock and data. If you're configuring from such a remote source - by the looks of the FX3 solution it's going to be quite a lot further from the FPGA than ideal - then 25MHz sounds a little punchy to me, regardless of the 133MHz max speed supported by Cyclone III. 

 

What does the relative timing between DCLK and DATA0 look like at the FPGA? 

 

Cheers, 

Alex
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Altera_Forum
Honored Contributor II
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It was in fact a timing issue between DCLK and DATA0. It turns out I missed a setting in the FX3 firmware that changed it to clock the data out on the Positive Edge rather than the Negative Edge. 

 

Thanks for the quick reply's.
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Altera_Forum
Honored Contributor II
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Hi, 

RickyThomson, I would like to know if the passive serial configuration by Cypress FX3 has worked successfully. I could do this passive serial using xmega microcontroller and I may need this FX3 setup later. 

 

Thanks
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Altera_Forum
Honored Contributor II
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Hey Sherif123, 

 

Yeah I was able to get it up and running. I actually found the following quite helpful... however this is for Xilinx FPGA for using it with an Altera took a bit of fiddling. 

 

http://www.cypress.com/documentation/application-notes/an84868-configuring-fpga-over-usb-using-cypress-ez-usb-fx3 

 

Kind Regards
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Altera_Forum
Honored Contributor II
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Hi RickyThomson, 

Thank you for your reply. 

I believe you used some GPIOs from the FX3 chips as control input and output to handle nStatus and nConfig. I think you also used some pins as SPI to handle the DCLK and DATA, right??
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Altera_Forum
Honored Contributor II
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Yeah that's correct, you set it all up in the FX3 firmware and the GPIF II.

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