Hi Iam workign with Cyclone v FPGA.
I am using DCFIFO from Quartus IP mapped to avalon mm interface where write side of FIFO is connected to avalon mm and read side is to the custom IP in QSYS system. I need a condition such that once FIFO is full with continuose writes, the avalon mm should wait until the FIFO is read from custom IP side (ie FIFO wrfull is deasserted )such that data write happens after that. How can I acheive this ? How to manipulate Avalon mm bus writes ?
Yes, you can do that using some logic in your custom component.
- Interface your DCFIFO and custom IP.
- Write a logic in custom IP to control DCFIFO read/write.
Refer below links design example and DCFIFO & avalon mm user guides.
A slave asserts wait request when unable to respond to a read or write request. Forces the master to wait until the interconnect is ready to proceed with the transfer.
You have should have wait logic in slave design to control it.
Please open a new case for further Query.