Using M4K mem for large shift registers

[Altera_Forum]

Hi 

I am trying to define a Large SR and want it to be implemented with memory and not Logical elements (otherwise it will not fit the device)   what should I add to my verilog code and what settings in the Quartus should I change in order to do that?   all my atteps so far had failed   :confused:                +++++++ +++++++++++++++++++++++++++++++++++++++++++++     (* ramstyle = "M4K" *) reg [15:0] InLine[2677:0];     //################ InData to Shift Reg# #########################    always@(negedge Rx_clk_A) // Shift Reg for the incoming data  begin // S.R. starts only when "write_port_A" is high   if ( write_port_A ) // i.e. valid recording condition for HDR + Image  begin  for (I=0 ; I<2677 ; I=I+1)  begin  InLine[I+1] <= InLine[I];  InLine[0] <= l[15:0];  //InLine[0] <= Danny_LinkA_Data;  end      end  end

[Altera_Forum]

You could start by using ALTSHIFT_TAPS megafunction.  

(http://www.altera.com/literature/ug/ug_alt_shift_taps.pdf)

[Altera_Forum]

Thanks I will try that also. 

but is this the write syntex to tell the quartus to implement this with a memory block? (* ramstyle = "M4K" *) reg [15:0] InLine[2677:0];   to achive that is there any settings I should change inthe quartus?   Urilis

[Altera_Forum]

In order to implement a simple shift-register, you should make an structured description of hardware. First, describe your RAM Block as a single module. 

 Shift Register can be implemented as a Circular Buffer with a FIFO behaviour, where input data are writen in head address and output data is read from tail addresss.   Read and write address generators can be implemented with  mod-N counters, each one pre-loaded with 0 and N-1 respectively, N is the shift-register size.

[Altera_Forum]

According to the Quartus software manual, a shiftregister in RAM (an ALTSHIFT_TAPS megafunction) can be inferred from a behavioural description. With default settings, no additional synthesis attribute is required for a sufficient large shift register. 

 As you reported, this method seems not to work with your code, but I don't know why. You may try to reproduce the suggested example more exactly.  The Quartus manual mentions several conditions for succesful SR inference:   --- Quote Start ---  To be detected, all the shift registers must have the following characteristics: &#9632; Use the same clock and clock enable &#9632; Do not have any other secondary signals &#9632; Have equally spaced taps that are at least three registers apart  --- Quote End ---    I tried with the Verilog template for one-bit wide, n-bit long shift register. It's always implemented in RAM, unless I disabled SR recognitaion for the module. (* altera_attribute = "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF" *)