Using Numonyx P33 TSOP for CIII AP Config

[Altera_Forum]

Hello, 

 I would like some clarification on the Cyclone III AP configuration using the Numonyx P33 flash memory in the TSOP package. The Altera documentation seems to contradict itself.  Here is the excerpt from the Cyclone III Handbook Vol. 1 Chapter 10 Page 10-25:    You must refer to the respective flash datasheets to check for supported speed grades and package options. For example, the Numonyx P30 and P33 families have only a single speed grade at 40 MHz. The synchronous burst read operation is permitted with all options of the P30 and P33 256-Mbit Thin Small Outline Package (TSOP) package when the clock frequency does not exceed 40 MHz and the P30 device does not operate below a minimum VCC of 1.85 V. Therefore, the P30 and P33 FBGA packages and only 256-Mbit TSOP devices are supported for the AP configuration scheme at this time. However, they do not support 40 MHz on the TSOP packages. Therefore, the P30 and P33 FBGA packages are supported for the AP configuration scheme while the TSOP packages are not supported.  I have looked through the datasheet for the Numonyx part and it appears to say that the TSOP part will work at 40 MHz and the FBGA part will work at 52 MHz. The Cyclone DCLK signal is specified to be 30 MHz (typically) and 40 MHz (maximum). It seems to me that the TSOP part would work, but maybe I am missing something.  Any insight?? :confused::confused::confused:

[Altera_Forum]

Hey, 

 I have the exact same question. The Cyclone III datasheet sounds like it they say it will not work, but then defers the reader to the manufacturer datahsheet. So then I read the manufacturer datasheet and its not easily determined what the speed of the part is.  From the Numonyx™ Axcell™ Embedded Memory (P30-65nm) datasheet timing parameters that are affected by TSOP package are: R1 tAVAV Read cycle time R2 tAVQV Address to output valid R3 tELQV CE# low to output valid R103 tVLQV ADV# low to output valid  Additonal info seems like the master controller can adjust performance by the latency count? Latency count 3= Less than or equal to 40Mhz Latency count 4= Less than or equal to 52Mhz  Since Altera provides hard IP and associated megafunctions, it would be nice if they get more specific and state which timing parameters exactly are key to determining why the TSOP would not work.   Telling users to look at themanufacturer's datasheet is confusing since depending on the settings it can be 40Mhz or 52 Mhz. It would help people who are not familiar with using FLASH memory for FPGA programming to spell it out for newbies.   Hope somebody can clarify the issue.

[Altera_Forum]

Hi, 

 The answer from Altera for specific flashes:  P30 JS28F256P30B95 TSOP ----SUPPORTED P30 JS28F256P30BF TSOP ----SUPPORTED BY NOVEMBER P30 PC28F256P30B85 FBGA ----SUPPORTED P30 PC28F256P30BF FBGA ----SUPPORTED BY NOVEMBER   P33 JS28F256P33B95 TSOP ----SUPPORTED P33 JS28F256P33BF TSOP ----IN INVESTIGATION  P33 PC28F256P33B85 FBGA ----SUPPORTED P33 PC28F256P33BF FBGA ----IN INVESTIGATION  I hope it helps you,  Best regards, Kest